commit 586150bf931c8cc270e1e86173e96f8ebeb1f8fb Author: jb Date: Thu Feb 5 08:24:50 2009 +0000 move nes into the sources/NES directory diff --git a/data/MegaMan.nes b/data/MegaMan.nes new file mode 100644 index 0000000..a71264a Binary files /dev/null and b/data/MegaMan.nes differ diff --git a/data/dk1.nes b/data/dk1.nes new file mode 100644 index 0000000..cb74aa9 Binary files /dev/null and b/data/dk1.nes differ diff --git a/data/dk2.nes b/data/dk2.nes new file mode 100644 index 0000000..eb3a5da Binary files /dev/null and b/data/dk2.nes differ diff --git a/data/dk3.nes b/data/dk3.nes new file mode 100644 index 0000000..9b9bb35 Binary files /dev/null and b/data/dk3.nes differ diff --git a/data/smb1.nes b/data/smb1.nes new file mode 100644 index 0000000..7a05208 Binary files /dev/null and b/data/smb1.nes differ diff --git a/data/testsuite/blargg_cpu_tests/official.nes b/data/testsuite/blargg_cpu_tests/official.nes new file mode 100644 index 0000000..5103f0f Binary files /dev/null and b/data/testsuite/blargg_cpu_tests/official.nes differ diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/palette_ram.nes b/data/testsuite/blargg_ppu_tests_2005.09.15b/palette_ram.nes new file mode 100644 index 0000000..878b321 Binary files /dev/null and b/data/testsuite/blargg_ppu_tests_2005.09.15b/palette_ram.nes differ diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/power_up_palette.nes b/data/testsuite/blargg_ppu_tests_2005.09.15b/power_up_palette.nes new file mode 100644 index 0000000..8964506 Binary files /dev/null and b/data/testsuite/blargg_ppu_tests_2005.09.15b/power_up_palette.nes differ diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/readme.txt b/data/testsuite/blargg_ppu_tests_2005.09.15b/readme.txt new file mode 100644 index 0000000..0222230 --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/readme.txt @@ -0,0 +1,74 @@ +NTSC NES PPU Tests +------------------ +These ROMs test a few aspects of the NTSC NES PPU operation. They have been +tested on an actual NES and all give a passing result. I wrote them to verify +that my NES emulator's PPU was working properly. + +Each ROM runs several tests and reports a result code on screen and by beeping +a number of times. A result code of 1 always indicates that all tests were +passed; see below for the meaning of other codes for each test. + +The main source code for each test is included, and most tests are clearly +divided into sections. Some of the common support code is included, but not +all, since it runs on a custom setup. Contact me if you want to assemble the +tests yourself. + +Shay Green (swap to e-mail) + + +palette_ram +----------- +PPU palette RAM read/write and mirroring test + +1) Tests passed +2) Palette read shouldn't be buffered like other VRAM +3) Palette write/read doesn't work +4) Paletteshould be mirrored within $3f00-$3fff +5) Write to $10 should be mirrored at $00 +6) Write to $00 should be mirrored at $10 + + +power_up_palette +---------------- +Reports whether initial values in palette at power-up match those +that my NES has. These values are probably unique to my NES. + +1) Palette matches +2) Palette differs from table + + +sprite_ram +---------- +Tests sprite RAM access via $2003, $2004, and $4014 + +1) Tests passed +2) Basic read/write doesn't work +3) Address should increment on $2004 write +4) Address should not increment on $2004 read +5) Third sprite bytes should be masked with $e3 on read +6) $4014 DMA copy doesn't work at all +7) $4014 DMA copy should start at value in $2003 and wrap +8) $4014 DMA copy should leave value in $2003 intact + + +vbl_clear_time +-------------- +The VBL flag ($2002.7) is cleared by the PPU around 2270 CPU clocks +after NMI occurs. + +1) Tests passed +2) VBL flag cleared too soon +3) VBL flag cleared too late + + +vram_access +----------- +Tests PPU VRAM read/write and internal read buffer operation + +1) Tests passed +2) VRAM reads should be delayed in a buffer +3) Basic Write/read doesn't work +4) Read buffer shouldn't be affected by VRAM write +5) Read buffer shouldn't be affected by palette write +6) Palette read should also read VRAM into read buffer +7) "Shadow" VRAM read unaffected by palette transparent color mirroring diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/palette_ram.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/palette_ram.asm new file mode 100644 index 0000000..d65e956 --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/palette_ram.asm @@ -0,0 +1,106 @@ +; PPU palette RAM read/write and mirroring test +; to do: check that upper two bits aren't stored + + .include "prefix_ppu.a" + +; Set VRAM address to $3f00 + X +; Preserved: A, X, Y +set_pal_addr: + pha + bit $2002 + lda #$3f + sta $2006 + txa + sta $2006 + pla + rts + +; Set palette entry X to A +; Preserved: A, X, Y +set_pal_entry: + jsr set_pal_addr + sta $2007 + rts + +; Read palette entry X into A +; Preserved: X, Y +get_pal_entry: + jsr set_pal_addr + lda $2007 + and #$3f + rts + +reset: + lda #50 + jsr delay_msec + + jsr wait_vbl + lda #0 + sta $2000 + sta $2001 + + lda #2;) Palette read shouldn't be buffered like other VRAM + sta result + ldx #$00 + lda #$12 + jsr set_pal_entry + lda #$34 + sta $2007 + jsr get_pal_entry + lda $2007 + cmp #$12 + jsr error_if_eq + + lda #3;) Palette write/read doesn't work + sta result + ldx #$00 + lda #$34 + jsr set_pal_entry + jsr get_pal_entry + lda $2007 + cmp #$34 + jsr error_if_ne + + lda #4;) Palette should be mirrored within $3f00-$3fff + sta result + ldx #$00 + lda #$12 + jsr set_pal_entry + ldx #$e0 + lda #$34 + jsr set_pal_entry + ldx #$00 + jsr get_pal_entry + cmp #$34 + jsr error_if_ne + + lda #5;) Write to $10 should be mirrored at $00 + sta result + ldx #$00 + lda #$12 + jsr set_pal_entry + ldx #$10 + lda #$34 + jsr set_pal_entry + ldx #$00 + jsr get_pal_entry + cmp #$34 + jsr error_if_ne + + lda #6;) Write to $00 should be mirrored at $10 + sta result + ldx #$10 + lda #$12 + jsr set_pal_entry + ldx #$00 + lda #$34 + jsr set_pal_entry + ldx #$10 + jsr get_pal_entry + cmp #$34 + jsr error_if_ne + + lda #1;) Tests passed + sta result + jmp report_final_result + diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/power_up_palette.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/power_up_palette.asm new file mode 100644 index 0000000..1fe0307 --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/power_up_palette.asm @@ -0,0 +1,35 @@ +; Reports whether initial values in palette at power-up match those +; that my NES has. These values are probably unique to my NES. + + .include "prefix_ppu.a" + +reset: + lda #50 + jsr delay_msec + + jsr wait_vbl + lda #0 + sta $2000 + sta $2001 + + lda #2;) Palette differs from table + sta result + lda #$3f + sta $2006 + lda #$00 + sta $2006 + ldx #0 +: lda $2007 + cmp table,x + jsr error_if_ne + inx + cpx #$20 + bne - + + lda #1;) Palette matches + sta result + jmp report_final_result + +table: + .db $09,$01,$00,$01,$00,$02,$02,$0D,$08,$10,$08,$24,$00,$00,$04,$2C + .db $09,$01,$34,$03,$00,$04,$00,$14,$08,$3A,$00,$02,$00,$20,$2C,$08 diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/prefix_ppu.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/prefix_ppu.asm new file mode 100644 index 0000000..a93e211 --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/prefix_ppu.asm @@ -0,0 +1,48 @@ +; Prefix included at the beginning of each test. Defines vectors +; and other things for custom devcart loader. +; +; Reset vector points to "reset". +; NMI points to "nmi" if defined, otherwise default_nmi. +; IRQ points to "irq" if defined, otherwise default_irq. + +default_nmi: + rti + +default_irq: + bit $4015 + rti + +; Delays for almost A milliseconds (A * 0.999009524 msec) +; Preserved: X, Y +delay_msec: + +; Delays for almost 'A / 10' milliseconds (A * 0.099453968 msec) +; Preserved: X, Y +delay_01_msec: + +; Variable delay. All calls include comment stating number of clocks +; used, including the setup code in the caller. +delay_yaNN: + +; Report value in low-mem variable 'result' as number of beeps and +; code printed to console, then jump to forever. +report_final_result: + +; Disable IRQ and NMI then loop endlessly. +forever: + + +; Report error if last result was non-zero +error_if_ne: + bne error_if_ + rts + +; Report error if last result was zero +error_if_eq: + beq error_if_ + rts + +; Report error +error_if_: + jmp report_final_result + diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/sprite_ram.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/sprite_ram.asm new file mode 100644 index 0000000..b6685ee --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/sprite_ram.asm @@ -0,0 +1,131 @@ +; Tests sprite RAM access via $2003, $2004, and $4014 + + .include "prefix_ppu.a" + +sprites = $200 + +reset: + lda #50 + jsr delay_msec + + jsr wait_vbl + lda #0 + sta $2000 + sta $2001 + + lda #2;) Basic read/write doesn't work + sta result + lda #0 + sta $2003 + lda #$12 + sta $2004 + lda #0 + sta $2003 + lda $2004 + cmp #$12 + jsr error_if_ne + + lda #3;) Address should increment on $2004 write + sta result + lda #0 + sta $2003 + lda #$12 + sta $2004 + lda #$34 + sta $2004 + lda #1 + sta $2003 + lda $2004 + cmp #$34 + jsr error_if_ne + + lda #4;) Address should not increment on $2004 read + sta result + lda #0 + sta $2003 + lda #$12 + sta $2004 + lda #$34 + sta $2004 + lda #0 + sta $2003 + lda $2004 + lda $2004 + cmp #$34 + jsr error_if_eq + + lda #5;) Third sprite bytes should be masked with $e3 on read + sta result + lda #3 + sta $2003 + lda #$ff + sta $2004 + lda #3 + sta $2003 + lda $2004 + cmp #$e3 + jsr error_if_eq + + lda #6;) $4014 DMA copy doesn't work at all + sta result + ldx #0 ; set up data to copy from +: lda test_data,x + sta sprites,x + inx + cpx #4 + bne - + lda #0 ; dma copy + sta $2003 + lda #$02 + sta $4014 + ldx #0 ; set up data to copy from +: stx $2003 + lda $2004 + cmp test_data,x + jsr error_if_ne + inx + cpx #4 + bne - + + lda #7;) $4014 DMA copy should start at value in $2003 and wrap + sta result + ldx #0 ; set up data to copy from +: lda test_data,x + sta sprites,x + inx + cpx #4 + bne - + lda #1 ; dma copy + sta $2003 + lda #$02 + sta $4014 + ldx #1 ; set up data to copy from +: stx $2003 + lda $2004 + cmp sprites - 1,x + jsr error_if_ne + inx + cpx #5 + bne - + + lda #8;) $4014 DMA copy should leave value in $2003 intact + sta result + lda #1 ; dma copy + sta $2003 + lda #$02 + sta $4014 + lda #$ff + sta $2004 + lda #1 + sta $2003 + lda $2004 + cmp #$ff + jsr error_if_ne + + lda #1;) Tests passed + sta result + jmp report_final_result + +test_data: + .db $12,$82,$e3,$78 + \ No newline at end of file diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vbl_clear_time.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vbl_clear_time.asm new file mode 100644 index 0000000..dc3b22e --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vbl_clear_time.asm @@ -0,0 +1,48 @@ +; The VBL flag ($2002.7) is cleared by the PPU around 2270 CPU clocks +; after NMI occurs. + + .include "prefix_ppu.a" + +phase = 10 + +reset: + lda #100 + jsr delay_msec + + lda #1 + sta phase + + jsr wait_vbl + lda #$80 + sta $2000 + lda #$00 + sta $2001 + +wait: jmp wait + +nmi: ; 7 clocks for NMI vectoring + ldy #203 ; 2251 delay + lda #1 + jsr delay_ya1 + + dec phase ; 5 + bne + ; 3 + ; -1 + + lda $2002 ; read at 2268 + ldx #2;) VBL flag cleared too soon + stx result + and #$80 + jsr error_if_eq + jmp wait + +: bit <0 + lda $2002 ; read at 2272 + ldx #3;) VBL flag cleared too late + stx result + and #$80 + jsr error_if_ne + + lda #1;) Tests passed + sta result + jmp report_final_result diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vram_access.asm b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vram_access.asm new file mode 100644 index 0000000..a7c9a50 --- /dev/null +++ b/data/testsuite/blargg_ppu_tests_2005.09.15b/source/vram_access.asm @@ -0,0 +1,143 @@ +; Tests PPU VRAM read/write and internal read buffer operation + + .include "prefix_ppu.a" + +; Set VRAM addr to $2f00 + A +; Preserved: A, X, Y +set_vram_pos: + pha + lda #$2f + sta $2006 + pla + sta $2006 + rts + +reset: + lda #50 + jsr delay_msec + + jsr wait_vbl + lda #0 + sta $2000 + sta $2001 + + lda #2;) VRAM reads should be delayed in a buffer + sta result + lda #$00 + jsr set_vram_pos + lda #$12 + sta $2007 + lda #$34 + sta $2007 + lda #$00 + jsr set_vram_pos + lda $2007 + lda $2007 + cmp #$34 + jsr error_if_eq + + lda #3;) Basic Write/read doesn't work + sta result + lda #$00 + jsr set_vram_pos + lda #$56 + sta $2007 + lda #$00 + jsr set_vram_pos + lda $2007 + lda $2007 + cmp #$56 + jsr error_if_ne + + lda #4;) Read buffer shouldn't be affected by VRAM write + sta result + lda #$00 + jsr set_vram_pos + lda #$78 + sta $2007 + lda #$00 + jsr set_vram_pos + lda #$00 + lda $2007 ; buffer now contains $78 + lda #$12 + sta $2007 ; shouldn't affect buffer + lda $2007 + cmp #$78 + jsr error_if_ne + + lda #5;) Read buffer shouldn't be affected by palette write + sta result + lda #$00 + jsr set_vram_pos + lda #$9a + sta $2007 + lda #$00 + jsr set_vram_pos + lda $2007 ; buffer now contains $9a + lda #$3f + sta $2006 + lda #$00 + sta $2006 + lda #$34 + sta $2007 ; shouldn't affect buffer + lda #$01 ; change back to non-palette addr to enable buffer + jsr set_vram_pos + lda $2007 + cmp #$9a + jsr error_if_ne + + lda #6;) Palette read should also read VRAM into read buffer + sta result + lda #$12 + jsr set_vram_pos + lda #$9a + sta $2007 + lda $2007 + lda #$3f + sta $2006 + lda #$12 + sta $2006 + lda $2007 ; fills buffer with VRAM hidden by palette + lda #$13 ; change back to non-palette addr to enable buffer + jsr set_vram_pos + lda $2007 + cmp #$9a + jsr error_if_ne + + lda #7;) "Shadow" VRAM read unaffected by palette mirroring + sta result + lda #$04 + jsr set_vram_pos + lda #$12 + sta $2007 + lda #$14 + jsr set_vram_pos + lda #$34 + sta $2007 + lda #$3f + sta $2006 + lda #$04 + sta $2006 + lda $2007 ; fills buffer with VRAM hidden by palette + lda #$13 ; change back to non-palette addr to enable buffer + jsr set_vram_pos + lda $2007 + cmp #$12 + jsr error_if_ne + lda #$34 + sta $2007 + lda #$3f + sta $2006 + lda #$14 + sta $2006 + lda $2007 ; fills buffer with VRAM hidden by palette + lda #$13 ; change back to non-palette addr to enable buffer + jsr set_vram_pos + lda $2007 + cmp #$34 + jsr error_if_ne + + lda #1;) Tests passed + sta result + jmp report_final_result + diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/sprite_ram.nes b/data/testsuite/blargg_ppu_tests_2005.09.15b/sprite_ram.nes new file mode 100644 index 0000000..dfbb613 Binary files /dev/null and b/data/testsuite/blargg_ppu_tests_2005.09.15b/sprite_ram.nes differ diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/vbl_clear_time.nes b/data/testsuite/blargg_ppu_tests_2005.09.15b/vbl_clear_time.nes new file mode 100644 index 0000000..41c2450 Binary files /dev/null and b/data/testsuite/blargg_ppu_tests_2005.09.15b/vbl_clear_time.nes differ diff --git a/data/testsuite/blargg_ppu_tests_2005.09.15b/vram_access.nes b/data/testsuite/blargg_ppu_tests_2005.09.15b/vram_access.nes new file mode 100644 index 0000000..301518b Binary files /dev/null and b/data/testsuite/blargg_ppu_tests_2005.09.15b/vram_access.nes differ diff --git a/data/testsuite/nestest/nestest.nes b/data/testsuite/nestest/nestest.nes new file mode 100644 index 0000000..fc2a88c Binary files /dev/null and b/data/testsuite/nestest/nestest.nes differ diff --git a/data/testsuite/nestest/nestest.txt b/data/testsuite/nestest/nestest.txt new file mode 100644 index 0000000..6c3657c --- /dev/null +++ b/data/testsuite/nestest/nestest.txt @@ -0,0 +1,724 @@ + The ultimate NES CPU test ROM + ----------------------------- + + +V1.00 - 09/06/04 + +By: Kevin Horton + + +--- + + +What it is: + +This here is a pretty much all inclusive test suite for a NES CPU. +It was designed to test almost every combination of flags, instructions, +and registers. Some of these tests are very difficult, and so far, +Nesten and Nesticle failed it. Nintendulator passes, as does a real +NES (naturally). I haven't tested it with any more emualtors yet. + +I attempted to check the states of all flags after most instructions. +For example, CPY and CMP shouldn't affect the overflow flag, while SBC +and ADC should. Likewise, all forms of wrapping ARE tested for- zeropage +wrapping being the tests most emulators fail. + +i.e. + +LDA #001h +LDA 0ffh,X ;indexed zeropage read + +should read the byte from 000h... NOT 0100h. This is because zeropage +instructions cannot cross a page boundary. + +--- + +How to work it good: + +Simply run the .NES ROM on your emulator of choice. You can select a single +test to run, or you can run ALL tests in sequence by selecting the +appropriate option. + +Pressing Select will change pages and allow testing "invalid" opcodes. +Be aware that these will crash alot of emulators Nesten. + +Once a test completes, the result will be "OK" if the test passes, or a +2 digit hex number which indicates a failure of some kind. A list is +provided below for the failure and its cause. For a more detailed reason +for the failure, you should check out the .ASM file included with this +document. + +If the entire page of tests succeeds, "OK" will be displayed next to the +first entry on the page. If one or more tests fails, "Er" will be displayed +instead. + +--- + +NSF player testing: + +This ROM is set up to be usable inside an NSF player. It outputs the +results of the test audially. + +--- + +Emulator authors: + +This test program, when run on "automation", (i.e. set your program counter +to 0c000h) will perform all tests in sequence and shove the results of +the tests into locations 02h and 03h. + +--- + +Final notes: + +The hex numbers shown on the screen (or stored in the above mentioned +memory locations) are of the LAST test that failed in the group tested. +This means, there could be multiple failures in one or more groups. This +wasn't the best solution, but since there are close to 400 tests performed, +any other way wouldn't have had acceptable memory usage. So long as your +emulator bugs are fixed and the numbers are getting smaller, you're doing +good :-) + + +---------------------------------------- + +Test failure codes and what they mean: + +(byte 02h only) + +000h - tests completed successfully + +branch tests +------------ +001h - BCS failed to branch +002h - BCS branched when it shouldn't have +003h - BCC branched when it shouldn't have +004h - BCC failed to branch +005h - BEQ failed to branch +006h - BEQ branched when it shouldn't have +007h - BNE failed to branch +008h - BNE branched when it shouldn't have +009h - BVS failed to branch +00Ah - BVC branched when it shouldn't have +00Bh - BVC failed to branch +00Ch - BVS branched when it shouldn't have +00Dh - BPL failed to branch +00Eh - BPL branched when it shouldn't have +00Fh - BMI failed to branch +010h - BMI branched when it shouldn't have + +flag tests +---------- +011h - PHP/flags failure (bits set) +012h - PHP/flags failure (bits clear) +013h - PHP/flags failure (misc bit states) +014h - PLP/flags failure (misc bit states) +015h - PLP/flags failure (misc bit states) +016h - PHA/PLA failure (PLA didn't affect Z and N properly) +017h - PHA/PLA failure (PLA didn't affect Z and N properly) + +immediate instruction tests +--------------------------- +018h - ORA # failure +019h - ORA # failure +01Ah - AND # failure +01Bh - AND # failure +01Ch - EOR # failure +01Dh - EOR # failure +01Eh - ADC # failure (overflow/carry problems) +01Fh - ADC # failure (decimal mode was turned on) +020h - ADC # failure +021h - ADC # failure +022h - ADC # failure +023h - LDA # failure (didn't set N and Z correctly) +024h - LDA # failure (didn't set N and Z correctly) +025h - CMP # failure (messed up flags) +026h - CMP # failure (messed up flags) +027h - CMP # failure (messed up flags) +028h - CMP # failure (messed up flags) +029h - CMP # failure (messed up flags) +02Ah - CMP # failure (messed up flags) +02Bh - CPY # failure (messed up flags) +02Ch - CPY # failure (messed up flags) +02Dh - CPY # failure (messed up flags) +02Eh - CPY # failure (messed up flags) +02Fh - CPY # failure (messed up flags) +030h - CPY # failure (messed up flags) +031h - CPY # failure (messed up flags) +032h - CPX # failure (messed up flags) +033h - CPX # failure (messed up flags) +034h - CPX # failure (messed up flags) +035h - CPX # failure (messed up flags) +036h - CPX # failure (messed up flags) +037h - CPX # failure (messed up flags) +038h - CPX # failure (messed up flags) +039h - LDX # failure (didn't set N and Z correctly) +03Ah - LDX # failure (didn't set N and Z correctly) +03Bh - LDY # failure (didn't set N and Z correctly) +03Ch - LDY # failure (didn't set N and Z correctly) +03Dh - compare(s) stored the result in a register (whoops!) +071h - SBC # failure +072h - SBC # failure +073h - SBC # failure +074h - SBC # failure +075h - SBC # failure + + +implied instruction tests +------------------------- +03Eh - INX/DEX/INY/DEY did something bad +03Fh - INY/DEY messed up overflow or carry +040h - INX/DEX messed up overflow or carry +041h - TAY did something bad (changed wrong regs, messed up flags) +042h - TAX did something bad (changed wrong regs, messed up flags) +043h - TYA did something bad (changed wrong regs, messed up flags) +044h - TXA did something bad (changed wrong regs, messed up flags) +045h - TXS didn't set flags right, or TSX touched flags and it shouldn't have + +stack tests +----------- +046h - wrong data popped, or data not in right location on stack +047h - JSR didn't work as expected +048h - RTS/JSR shouldn't have affected flags +049h - RTI/RTS didn't work right when return addys/data were manually pushed + +accumulator tests +----------------- +04Ah - LSR A failed +04Bh - ASL A failed +04Ch - ROR A failed +04Dh - ROL A failed + +(indirect,x) tests +------------------ +058h - LDA didn't load the data it expected to load +059h - STA didn't store the data where it was supposed to +05Ah - ORA failure +05Bh - ORA failure +05Ch - AND failure +05Dh - AND failure +05Eh - EOR failure +05Fh - EOR failure +060h - ADC failure +061h - ADC failure +062h - ADC failure +063h - ADC failure +064h - ADC failure +065h - CMP failure +066h - CMP failure +067h - CMP failure +068h - CMP failure +069h - CMP failure +06Ah - CMP failure +06Bh - CMP failure +06Ch - SBC failure +06Dh - SBC failure +06Eh - SBC failure +06Fh - SBC failure +070h - SBC failure + +zeropage tests +-------------- +076h - LDA didn't set the flags properly +077h - STA affected flags it shouldn't +078h - LDY didn't set the flags properly +079h - STY affected flags it shouldn't +07Ah - LDX didn't set the flags properly +07Bh - STX affected flags it shouldn't +07Ch - BIT failure +07Dh - BIT failure +07Eh - ORA failure +07Fh - ORA failure +080h - AND failure +081h - AND failure +082h - EOR failure +083h - EOR failure +084h - ADC failure +085h - ADC failure +086h - ADC failure +087h - ADC failure +088h - ADC failure +089h - CMP failure +08Ah - CMP failure +08Bh - CMP failure +08Ch - CMP failure +08Dh - CMP failure +08Eh - CMP failure +08Fh - CMP failure +090h - SBC failure +091h - SBC failure +092h - SBC failure +093h - SBC failure +094h - SBC failure +095h - CPX failure +096h - CPX failure +097h - CPX failure +098h - CPX failure +099h - CPX failure +09Ah - CPX failure +09Bh - CPX failure +09Ch - CPY failure +09Dh - CPY failure +09Eh - CPY failure +09Fh - CPY failure +0A0h - CPY failure +0A1h - CPY failure +0A2h - CPY failure +0A3h - LSR failure +0A4h - LSR failure +0A5h - ASL failure +0A6h - ASL failure +0A7h - ROL failure +0A8h - ROL failure +0A9h - ROR failure +0AAh - ROR failure +0ABh - INC failure +0ACh - INC failure +0ADh - DEC failure +0AEh - DEC failure +0AFh - DEC failure + +Absolute tests +-------------- +0B0h - LDA didn't set the flags properly +0B1h - STA affected flags it shouldn't +0B2h - LDY didn't set the flags properly +0B3h - STY affected flags it shouldn't +0B4h - LDX didn't set the flags properly +0B5h - STX affected flags it shouldn't +0B6h - BIT failure +0B7h - BIT failure +0B8h - ORA failure +0B9h - ORA failure +0BAh - AND failure +0BBh - AND failure +0BCh - EOR failure +0BDh - EOR failure +0BEh - ADC failure +0BFh - ADC failure +0C0h - ADC failure +0C1h - ADC failure +0C2h - ADC failure +0C3h - CMP failure +0C4h - CMP failure +0C5h - CMP failure +0C6h - CMP failure +0C7h - CMP failure +0C8h - CMP failure +0C9h - CMP failure +0CAh - SBC failure +0CBh - SBC failure +0CCh - SBC failure +0CDh - SBC failure +0CEh - SBC failure +0CFh - CPX failure +0D0h - CPX failure +0D1h - CPX failure +0D2h - CPX failure +0D3h - CPX failure +0D4h - CPX failure +0D5h - CPX failure +0D6h - CPY failure +0D7h - CPY failure +0D8h - CPY failure +0D9h - CPY failure +0DAh - CPY failure +0DBh - CPY failure +0DCh - CPY failure +0DDh - LSR failure +0DEh - LSR failure +0DFh - ASL failure +0E0h - ASL failure +0E1h - ROR failure +0E2h - ROR failure +0E3h - ROL failure +0E4h - ROL failure +0E5h - INC failure +0E6h - INC failure +0E7h - DEC failure +0E8h - DEC failure +0E9h - DEC failure + +(indirect),y tests +------------------ +0EAh - LDA didn't load what it was supposed to +0EBh - read location should've wrapped around ffffh to 0000h +0ECh - should've wrapped zeropage address +0EDh - ORA failure +0EEh - ORA failure +0EFh - AND failure +0F0h - AND failure +0F1h - EOR failure +0F2h - EOR failure +0F3h - ADC failure +0F4h - ADC failure +0F5h - ADC failure +0F6h - ADC failure +0F7h - ADC failure +0F8h - CMP failure +0F9h - CMP failure +0FAh - CMP failure +0FBh - CMP failure +0FCh - CMP failure +0FDh - CMP failure +0FEh - CMP failure + +(error byte location 03h starts here) + +000h - no error, all tests pass +001h - SBC failure +002h - SBC failure +003h - SBC failure +004h - SBC failure +005h - SBC failure +006h - STA failure +007h - JMP () data reading didn't wrap properly (this fails on a 65C02) + +zeropage,x tests +---------------- +008h - LDY,X failure +009h - LDY,X failure +00Ah - STY,X failure +00Bh - ORA failure +00Ch - ORA failure +00Dh - AND failure +00Eh - AND failure +00Fh - EOR failure +010h - EOR failure +011h - ADC failure +012h - ADC failure +013h - ADC failure +014h - ADC failure +015h - ADC failure +016h - CMP failure +017h - CMP failure +018h - CMP failure +019h - CMP failure +01Ah - CMP failure +01Bh - CMP failure +01Ch - CMP failure +01Dh - SBC failure +01Eh - SBC failure +01Fh - SBC failure +020h - SBC failure +021h - SBC failure +022h - LDA failure +023h - LDA failure +024h - STA failure +025h - LSR failure +026h - LSR failure +027h - ASL failure +028h - ASL failure +029h - ROR failure +02Ah - ROR failure +02Bh - ROL failure +02Ch - ROL failure +02Dh - INC failure +02Eh - INC failure +02Fh - DEC failure +030h - DEC failure +031h - DEC failure +032h - LDX,Y failure +033h - LDX,Y failure +034h - STX,Y failure +035h - STX,Y failure + +absolute,y tests +---------------- +036h - LDA failure +037h - LDA failure to wrap properly from ffffh to 0000h +038h - LDA failure, page cross +039h - ORA failure +03Ah - ORA failure +03Bh - AND failure +03Ch - AND failure +03Dh - EOR failure +03Eh - EOR failure +03Fh - ADC failure +040h - ADC failure +041h - ADC failure +042h - ADC failure +043h - ADC failure +044h - CMP failure +045h - CMP failure +046h - CMP failure +047h - CMP failure +048h - CMP failure +049h - CMP failure +04Ah - CMP failure +04Bh - SBC failure +04Ch - SBC failure +04Dh - SBC failure +04Eh - SBC failure +04Fh - SBC failure +050h - STA failure + +absolute,x tests +---------------- +051h - LDY,X failure +052h - LDY,X failure (didn't page cross) +053h - ORA failure +054h - ORA failure +055h - AND failure +056h - AND failure +057h - EOR failure +058h - EOR failure +059h - ADC failure +05Ah - ADC failure +05Bh - ADC failure +05Ch - ADC failure +05Dh - ADC failure +05Eh - CMP failure +05Fh - CMP failure +060h - CMP failure +061h - CMP failure +062h - CMP failure +063h - CMP failure +064h - CMP failure +065h - SBC failure +066h - SBC failure +067h - SBC failure +068h - SBC failure +069h - SBC failure +06Ah - LDA failure +06Bh - LDA failure (didn't page cross) +06Ch - STA failure +06Dh - LSR failure +06Eh - LSR failure +06Fh - ASL failure +070h - ASL failure +071h - ROR failure +072h - ROR failure +073h - ROL failure +074h - ROL failure +075h - INC failure +076h - INC failure +077h - DEC failure +078h - DEC failure +079h - DEC failure +07Ah - LDX,Y failure +07Bh - LDX,Y failure + +------------------------------------ + +Invalid opcode tests... all errors are reported in byte 03h unless +specified. + +NOP - "invalid" opcode tests (error byte 02h) +--------------------------------------------- +04Eh - absolute,X NOPs less than 3 bytes long +04Fh - implied NOPs affects regs/flags +050h - ZP,X NOPs less than 2 bytes long +051h - absolute NOP less than 3 bytes long +052h - ZP NOPs less than 2 bytes long +053h - absolute,X NOPs less than 3 bytes long +054h - implied NOPs affects regs/flags +055h - ZP,X NOPs less than 2 bytes long +056h - absolute NOP less than 3 bytes long +057h - ZP NOPs less than 2 bytes long + +LAX - "invalid" opcode tests +---------------------------- +07Ch - LAX (indr,x) failure +07Dh - LAX (indr,x) failure +07Eh - LAX zeropage failure +07Fh - LAX zeropage failure +080h - LAX absolute failure +081h - LAX absolute failure +082h - LAX (indr),y failure +083h - LAX (indr),y failure +084h - LAX zp,y failure +085h - LAX zp,y failure +086h - LAX abs,y failure +087h - LAX abs,y failure + +SAX - "invalid" opcode tests +---------------------------- +088h - SAX (indr,x) failure +089h - SAX (indr,x) failure +08Ah - SAX zeropage failure +08Bh - SAX zeropage failure +08Ch - SAX absolute failure +08Dh - SAX absolute failure +08Eh - SAX zp,y failure +08Fh - SAX zp,y failure + +SBC - "invalid" opcode test +--------------------------- +090h - SBC failure +091h - SBC failure +092h - SBC failure +093h - SBC failure +094h - SBC failure + +DCP - "invalid" opcode tests +---------------------------- +095h - DCP (indr,x) failure +096h - DCP (indr,x) failure +097h - DCP (indr,x) failure +098h - DCP zeropage failure +099h - DCP zeropage failure +09Ah - DCP zeropage failure +09Bh - DCP absolute failure +09Ch - DCP absolute failure +09Dh - DCP absolute failure +09Eh - DCP (indr),y failure +09Fh - DCP (indr),y failure +0A0h - DCP (indr),y failure +0A1h - DCP zp,x failure +0A2h - DCP zp,x failure +0A3h - DCP zp,x failure +0A4h - DCP abs,y failure +0A5h - DCP abs,y failure +0A6h - DCP abs,y failure +0A7h - DCP abs,x failure +0A8h - DCP abs,x failure +0A9h - DCP abs,x failure + +ISB - "invalid" opcode tests +---------------------------- +0AAh - DCP (indr,x) failure +0ABh - DCP (indr,x) failure +0ACh - DCP (indr,x) failure +0ADh - DCP zeropage failure +0AEh - DCP zeropage failure +0AFh - DCP zeropage failure +0B0h - DCP absolute failure +0B1h - DCP absolute failure +0B2h - DCP absolute failure +0B3h - DCP (indr),y failure +0B4h - DCP (indr),y failure +0B5h - DCP (indr),y failure +0B6h - DCP zp,x failure +0B7h - DCP zp,x failure +0B8h - DCP zp,x failure +0B9h - DCP abs,y failure +0BAh - DCP abs,y failure +0BBh - DCP abs,y failure +0BCh - DCP abs,x failure +0BDh - DCP abs,x failure +0BEh - DCP abs,x failure + +SLO - "invalid" opcode tests +---------------------------- +0BFh - SLO (indr,x) failure +0C0h - SLO (indr,x) failure +0C1h - SLO (indr,x) failure +0C2h - SLO zeropage failure +0C3h - SLO zeropage failure +0C4h - SLO zeropage failure +0C5h - SLO absolute failure +0C6h - SLO absolute failure +0C7h - SLO absolute failure +0C8h - SLO (indr),y failure +0C9h - SLO (indr),y failure +0CAh - SLO (indr),y failure +0CBh - SLO zp,x failure +0CCh - SLO zp,x failure +0CDh - SLO zp,x failure +0CEh - SLO abs,y failure +0CFh - SLO abs,y failure +0D0h - SLO abs,y failure +0D1h - SLO abs,x failure +0D2h - SLO abs,x failure +0D3h - SLO abs,x failure + +RLA - "invalid" opcode tests +---------------------------- +0D4h - RLA (indr,x) failure +0D5h - RLA (indr,x) failure +0D6h - RLA (indr,x) failure +0D7h - RLA zeropage failure +0D8h - RLA zeropage failure +0D9h - RLA zeropage failure +0DAh - RLA absolute failure +0DBh - RLA absolute failure +0DCh - RLA absolute failure +0DDh - RLA (indr),y failure +0DEh - RLA (indr),y failure +0DFh - RLA (indr),y failure +0E0h - RLA zp,x failure +0E1h - RLA zp,x failure +0E2h - RLA zp,x failure +0E3h - RLA abs,y failure +0E4h - RLA abs,y failure +0E5h - RLA abs,y failure +0E6h - RLA abs,x failure +0E7h - RLA abs,x failure +0E8h - RLA abs,x failure + +SRE - "invalid" opcode tests +---------------------------- +0E8h - SRE (indr,x) failure +0EAh - SRE (indr,x) failure +0EBh - SRE (indr,x) failure +0ECh - SRE zeropage failure +0EDh - SRE zeropage failure +0EEh - SRE zeropage failure +0EFh - SRE absolute failure +0F0h - SRE absolute failure +0F1h - SRE absolute failure +0F2h - SRE (indr),y failure +0F3h - SRE (indr),y failure +0F4h - SRE (indr),y failure +0F5h - SRE zp,x failure +0F6h - SRE zp,x failure +0F7h - SRE zp,x failure +0F8h - SRE abs,y failure +0F9h - SRE abs,y failure +0FAh - SRE abs,y failure +0FBh - SRE abs,x failure +0FCh - SRE abs,x failure +0FDh - SRE abs,x failure + + +RRA - "invalid" opcode tests +---------------------------- +001h - RRA (indr,x) failure +002h - RRA (indr,x) failure +003h - RRA (indr,x) failure +004h - RRA zeropage failure +005h - RRA zeropage failure +006h - RRA zeropage failure +007h - RRA absolute failure +008h - RRA absolute failure +009h - RRA absolute failure +00Ah - RRA (indr),y failure +00Bh - RRA (indr),y failure +00Ch - RRA (indr),y failure +00Dh - RRA zp,x failure +00Eh - RRA zp,x failure +00Fh - RRA zp,x failure +010h - RRA abs,y failure +011h - RRA abs,y failure +012h - RRA abs,y failure +013h - RRA abs,x failure +014h - RRA abs,x failure +015h - RRA abs,x failure + + + + + + + + +001h - +002h - +003h - +004h - +005h - +006h - +007h - +008h - +009h - +00Ah - +00Bh - +00Ch - +00Dh - +00Eh - +00Fh - +010h - + + +Todo: check to see if decimal mode is missing on CPU diff --git a/data/testsuite/nestress.nes b/data/testsuite/nestress.nes new file mode 100644 index 0000000..db668a6 Binary files /dev/null and b/data/testsuite/nestress.nes differ diff --git a/docs/nesdoc1.txt b/docs/nesdoc1.txt new file mode 100644 index 0000000..6be4320 --- /dev/null +++ b/docs/nesdoc1.txt @@ -0,0 +1,1106 @@ +v0.9 ASSEMBLEUR SUR NES + CRISPYSIX + +Lorsque j'ai commencé à m'interesser à la NES, j'ai constitué une sorte de journal +de bord avec de nombreuses notes. Au fur et à mesure de ces notes d'abord réparties +anarchiquement, il m'est venu l'idée d'en faire une sorte de compilation qui +pourrait aisément être réutilisé par d'autres personnes. Ainsi est née cette documentation. + +Je n'ai pas la prétention de vous apprendre à devenir des as en la matière +mais vu le peu de documents disponibles (en français du moins c'est le néant), je pense +que ce genre de choses sera loin d'être inutile pour ceux qui s'intéressent +encore à cette vieille machine. Attention la mise en page de cette doc est +chaotique mais a force on risque de s'y habituer... + + +Si vous avez choisi de commencer à vouloir créer vous même vos programmes en +assembleur en prenant la NES, je ne peux qu'approuver ce choix, même s'il ne s'agit pas +à mon avis d'une des machines les plus simples à comprendre et à programmer, c'est +une des mieux documentées, grâce à l'acharnement de quelques passionnés. +En plus comme beaucoup de personnes semblent aussi attirées par la Supernes ça ne +peut qu'être utile (famille de processeur,ect...), je trouve ça bien trop +compliqué pour l'instant faire quelque chose de concret au niveau des coprocesseurs. + +ASM HACKING -> Attention! Sur NES il est beaucoup plus délicat que sur SUPERNES, +au niveau de l'adressage, et en lisant cette doc vous devriez comprendre pourquoi. + +Note: Les adresses sont données en hexa avec un $ devant, les valeurs immédiates avec un #. +Bon il est possible que je fasse des petits ecarts involontaires mais dans l'ensemble c'est ça. + + +J'ai choisie de découper cette documentation en 2 parties bien distinctes. +Les points suivants seront abordés: + +Dans le premier fichier: + +- Brève presentation de la NES. + 1. -> Caractéristiques fondamentales + 2. -> Vues générales sur la mémoire centrale + +- Fonctionnnement du processeur 6502. + 1. -> Généralitées sur l'architecture et présentation des registres du processeur + 2. -> Généralitées sur les modes d'adressages utilisées par le 6502 + 3. -> Instructions détaillées avec leur fonctionnement + 4. -> Tableau détaillé des opcodes par ordre alphabetique + 5. -> Interruptions + +Dans le second fichier: + +- Fonctionnement de la PPU (Picture Processing Unit). + 1. -> Partage de la VRAM + 2. -> Tables des graphismes + 3. -> Tables de nommage + 4. -> Tables d'attribution + 5. -> Fonctionnement des palettes + 6. -> Fonctionnement des miroirs + 7. -> Scrolling de l'arrière plan + 8. -> Fonctionnement des sprites + 9. -> VBlank et HBlank + +- Fonctionnement des autres peripheriques. + 1. -> Pseudo-Audio Processing Unit + 2. -> Ports Joypads + +- Détails sur les registres de periphériques. + 1. -> Registres PPU + 2. -> Registres pAPU + 3. -> Registres Joypads + +- Autres choses utiles. + 1. -> Structure iNes + 2. -> Multi-Memory Controler + +- Détails sur les méthodes d'assemblage. + +- Epilogue. + + +Brève présentation de la NES: +---------------------------- + +Bon je vais pas refaire l'histoire de cette console ça n'a aucune importance ici. +Juste ce qui est nécessaire donc. La Famicom (nom japonais de la NES) est sortie en +1983 au Japon, fut immediatement un gros succès, sa commercialisation suivi alors +sous le nom de Nintendo Entertainment System logiquement aux Etats-Unis puis en Europe. + + 1. Caractéristiques fondamentales: + +La NES est architécturée autour d'un processeur 8 bits, le 2A03, variante du 6502. +Ce dernier est très en vogue dans les années 80 et équipe de nombreux micro-ordinateurs, +comme le C64. Egalement autre composant capital, le PPU pour l'affichage. +Si vous ouvrez une NES vous les apercevrez facilement puisque ce sont les 2 plus +gros composants de la carte mère. + + Détails techniques: +2 composants principaux: + +-Processeur central: 2A03 NMOS fabriqué par RICOH cadencé à 1,7897725 Mhz pour + la version NTSC et 1,773447 Mhz pour la version PAL (détaillé après). + Le processeur est cablé à 2 ko de RAM. +-Picture Processing Unit: Unité chargée de l'affichage des sprites et des arrières plan. Son utilisation + particulière sera détaillée plus tard. Elle dispose de 16 ko de VRAM et + 256 octets pour les sprites. + Autre: +-Capacitées sonores: La NES dispose de 5 voix sonores, 2 canaux de synthèses FM, un canal triangle + un canal de bruit, et un canal DMC (Delta Modulation Channel). + Le son est pris en charge par le processeur central. + + 2. Vues générales sur la mémoire: + +Toute la memoire de la NES est représentée sur une seule et même plage mémoire, +mais leur utilisation est bien différente... +En fait c'est assez simple à introduire et une fois que l'on à compris il n'est pas +nécessaire de revenir là-dessus. Voilà comment cela marche: +-de $0 à $7FF: Il s'agit de la RAM qui va servir pour le stockage des données (2 ko). +-de $800 à $1FFF: Miroirs de la RAM tous les #800 octets. +-de $2000 à $2007: Registres de la PPU +-de $2008 à $3FFF: Autres registres (miroirs des registres de la PPU tous les 8 octets) +-de $4000 à $4016: Registres de la pAPU et des manettes +-de $4017 à $4FFF: N/A +-de $5000 à $5FFF: Expansion +-de $6000 à $7FFF: Mémoire SRAM pour les sauvegardes +-de $8000 à $BFFF: PRG-ROM (code contenu dans la ROM) d'une taille de $4000 (16384) +-de $C000 à $FFFF: PRG-ROM d'une taille de $4000 (16384) + +L'utilisation de la VRAM est entièrement gérée par la PPU, inutile donc de l'aborder ici. +Les deux plages servant à lire du code instruction (PRG-ROM) ne sont pas forcement utilisables +linéairement. +Pour les données statiques graphiques (stockage du graphisme et des sprites) on utilise plus +souvent la CHR-ROM, dont le fonctionnement sera détaillé plus tard avec la PPU. +Pour le miroir de la mémoire centrale, voyez cela comme un alias: +écrire un octet l'adresse $0 l'écrit aussi à l'adresse $800, $1000 et $1800. +Remarque: grâce au MMC on peut faire varier considérablement la taille et la structure des données, +cependant la PRG-ROM restera de toute facon statique (son emplacement est fixé et définitif). + + +Fonctionnement du processeur 6502: +--------------------------------- + +Donc le processeur 6502 est dit 8 bits car ses registres de travail sont limités à une taille de 8 bits, +ce qui induit qu'il sera impossible de manipuler des valeur ayant une taille superieure à 8 bits. +Ca peut sembler très limitant au premier abord, mais en réalité...ça l'est réellement. +Cela va vraiment devenir un handicap dans le codage d'algorithmes de compression ou autre. +Cependant (et fort heureusement) le compteur ordinal (Program Counter) est lui en 16 bits. Celà limite +tout de même l'adressage à 64 ko mais pour pouvoir accéder à plus de mémoire on a recours au +MMC (Multi-Memory Controller), qui sera abordé plus tard. Les opérandes seront donc de 8 bits. + + 1. Généralitées sur l'architecture et présentation des registres du processeur: + +Le processeur 6502 est donc l'unique interface entre l'utilisateur et la machine. Il dispose d'un +jeu d'instructions capable de manipuler des données sur une zone d'adresse de 64 ko et +de 6 registres, 5 8-bits et un de 16 bits. + +Program Counter (compteur ordinal): C'est un registre 16 bits qui peut adresser toute la mémoire +disponible sur une plage de $0 à $FFFF. +Par defaut, il contient l'adresse de la prochaine instruction à +executer. En outre chaque instruction ne va pas agir de la même facon. +L'instruction LDA #$12 par exemple incrementera le compteur ordinal de 2. +Il est directement adréssé par des instructions nécessitant des adresses (STA,LDA,JSR,...). +En outre le compteur ordinal change à chaque instruction. + +Stack Register (pointeur de pile): Registre de 8 bits pointant sur le haut de la pile. +Normalement vous n'avez pas à vous en soucier. L'utilisation de la pile est quelque chose de très +pratique, comparable à une pile d'assiettes. Utiliser le plus souvent avec les instructions PHA (PUSH) +et PLA (POP), la pile permet de maitriser aisément les retours de fonctions par exemple. +En revanche attention car l'instruction JSR utilise la pile pour mémoriser l'adresse de retour. +Pour info, la pile est en fait la zone mémoire s'étendant dans la ram de $100 à $1FF. +A vous de faire attention de ne pas depasser sa capacité. +Note: il est parfois nécessaire d'initialiser la pile à $FF (Registre pointeur de pile). + +Processor Status (registre d'etat): Registre 8 bits qui a une importance capitale puisque qu'il +change en fonction du résultat des instructions, il va donc permettre d'implementer toutes les +structures conditionnelles, indispensables dans un programme. Pour comprendre son fonctionnement, +il faut voir chaque bits du registre d'etat comme une variable booléenne, qui peut prendre 2 valeurs +vrai ou faux. Voici comment il fonctionne: + + C - Bit 0, Carry Flag (Bit de retenu): comme son nom l'indique ce bit va permettre de mémoriser + si le résultat d'une opération est sujet à une retenue. Un exemple simple: + Imaginons que nous ajoutions 1 à 255, cela aura pour résultat 0 avec le bit de retenue à 1. + En outre d'autres instructions comme les instructions de rotation l'utilisent. + + Z - Bit 1, Zero Flag (Bit d'etat Zero): Ce bit est mis à 1 lorsque le resultat d'une instruction + est 0. + + I - Bit 2, Interrupt Disable Flag (Bit d'autorisation d'interruptions): Si ce bit est mis à 1 on bloque + les interruptions non masquables (NMI) venant des periphériques (détaillé en partie 5). + + D - Bit 3, Decimal Mode (Mode décimal): Si il est mis à 1 indique que l'on est en mode décimal. + Pas très utile car limite le nombre de combinaisons pour un octet à 255 valeurs. + De plus sur la version du 6502 utilisé sur NES, il n'existe pas de mode décimal effectif! + Donc activer ou désactiver ce flag ne servira à rien. + + B - Bit 4, Break Command (Bit de Break): Si une interruption est causée par l'instruction BRK, + ce bit est mis à 1, il est mis à 0 si il s'agit d'une interruption externe. + + V - Bit 6, Overflow Flag (Bit de depassement signé): Ce bit permet de simuler la retenue pour + 2 nombre pseudos signés. C'est a dire que l'on va prendre le calcul de 2 valeurs + sur 7 uniquement, le dernier servant au signe. Par exemple: 01111111+00000001=10000000 + -> ce calcul ne modifiera pas le flag C mais modifiera le flag V. + + N - Bit 7, Negative Flag (Bit de negation): Ce flag est tres lié au second, il sert au calcul de valeurs + signées. En fait ce bit est mis a 1 si le resultat contenu dans l'accumulateur à son bit 7 + mis à 1. + +Remarque: le bit #5 est inutilisé sur le 6502. + + Le registre d'état peut etre représenté de la façon suivante: + + +-----+-----+-----+-----+-----+-----+-----+-----+ + | | | | | | | | | + | N | V | | B | D | I | Z | C | + | | | | | | | | | + +-----+-----+-----+-----+-----+-----+-----+-----+ + +Les registres de travail (utilisables directement par l'utilisateur): + +Accumulator (Accumulateur) A: Il s'agit du registre de travail principal, puisque qu'il va être utilisé +par toutes les instructions utilisant l'unité arithmétique et logique du processeur. C'est à dire que +tous les calculs passeront necessairement par lui. + +Registre X: Utilisé pour les adressages indexés et le controle des boucles principalement. + +Registre Y: Comparable au registre X mais dispose de moins d'instructions et donc de fonctionnalitées. + + 2. Généralitées sur les modes d'adressages utilisées par le 6502: + +Les modes d'adressages qui vont être présentés ne sont pas forcement tous utilisés par les instructions +nécessitant une adresse. Il y en a 12 en tout sur le 6502. + +Voici de quoi il retourne: + + Adressage immédiat: S'utilise de la forme "#$??" où $?? est l'opérande l'hexa à charger par l'instruction. + Il s'agit du mode d'adressage le plus simple puisqu'on n'utilise pas le compteur ordinal. + Bien entendu il ne s'utilise qu'en lecture. + + Adressage absolu: Dans ce mode on utilise le compteur ordinal, la syntaxe est la suivante: "LDA aaaa" + où aaaa contient l'adresse de l'operande à charger dans l'accumulateur. + + Adressage page zero: Similaire au précédent mais là on utilise que 8 bits pour l'adresse, ce qui limite + l'adressage a la page mémoire 0 (cad de $0 à $FF), utile pour alléger le code. + + Adressage indirect absolu: La seule instruction a l'utiliser est l'instruction JMP. Sa syntaxe est "($aaaa)". + En fait l'adresse aaaa contient l'adresse de l'opérande. Attention ne pas oublier que le 6502 + fonctionne en mode Little Endian! Ainsi l'adresse pointe sur la seconde opérande de l'adresse, il faut + faire une permutation. + + Adressage absolu indexé: On va utiliser les registres X et Y pour ce type d'adressage. La syntaxe est la suivante: + "$aaaa, ?" où aaaa est l'adresse et ? est un registre X ou Y. Par exemple "LDA $1285,X" et X contenant 5 + donnera comme adresse $1285+$5=$128A. + + Adressage indexé page zero: Similaire a l'exemple precedent sauf que l'adresse ne s'étend que 8 bits. + + Adressage indexé indirect: La syntaxe de ce mode d'adressage est la suivante: "($aa,?)" où aa contient + l'adresse et ? le nom du registre (X ou Y) à ajouter a l'adresse pour obtenir l'adresse definitive + de l'opérande. + + Adressage indirect indexé: La syntaxe ressemble à la precedente: "($aa),?" sauf que on va d'abord chercher l'adresse + trouvé en aa et ensuite on y ajoute la valeur du registre ? pour obtenir l'adresse finale l'opérande. + + Adressage relatif: utilisé par les instructions de branchement (détaillées après). Il s'agit de considérer les + opérandes 8 bits passées a l'instruction comme des valeurs signées, cela va permettre d'effectuer + des branchements vers des instructions antérieures en mémoire. Il s'agit en fait d'incrémenter ou + décrementer le compteur ordinal avec l'opérande que l'on passe. + Exemple: 01111111=127 + 10000000=-128 + + Adressage implié: l'adressage n'en est en fait pas vraiment un puisqu'il est transparent dans l'instruction, + qui ne nécessite pas de valeurs en paramètre (juste la taille de l'opcode). + + +-------------------------------+---------------+ + |Adressage immédiat |#$?? | + |Adressage absolu |$???? | + |Adressage page zero |$?? | + |Adressage indirect absolu |($????) | + |Adressage absolu indexé |$????,X | + |Adressage indexé page zero |$??,X | + |Adressage indexé indirect |($??,X) | + |Adressage indirect indexé |($??),X | + |Adressage relatif |$?? ->signé | + |Adressage implié | | + +-------------------------------+---------------+ + +Remarque: on peut remplacer le registre X par le registre Y indifférament sauf pour certaines instructions. + + 3. Instructions détaillées avec leur fonctionnement: + + +Le processeur 6502 compte 56 mnémonics differents (comprenez noms d'instructions). En outre pour chaque instruction vue +certaines peuvent faire l'objet de plusieurs modes d'adressages differents. (leurs opcodes seront bien entendu différents). +Les modes d'adressages possibles par instruction seront détaillés dans la partie Opcodes. +Note: A=Accumulateur +Parenthèse: le langage machine (comprenez celui qui utilise les instructions) n'est absolument pas le plus bas niveau du +processeur. Lorsque l'on dit que le 6502 est cadencé à 1,773447 Mhz, ça signifie qu'il peut faire 1 million 773447 cycle +d'horloge par seconde, hors selon les instructions le nombre de cycle d'horloge varie relativement beaucoup selon les +instructions utilisées. Il existe des documentations sur le 6502 relativement complètes pour ce genre de choses. + +Voici les instructions disponibles dans l'ordre alphabetique: + +ADC - Add with Carry - +Flags afféctés: N,Z,C,V +Additionne A avec l'operande désignée par le mode d'adressage, ainsi que le bit de retenue +et place le resultat dans A. Selon les résultats les flags sont mis à jour. Si vous voulez effectuer +une addition vierge il ne faut pas oublier de remettre à zero le bit de retenue (C). + +AND - Logical AND (ET Logique) - +Flags afféctés: N,Z +Effectue un ET logique entre A et l'opérande désignée par le mode d'adressage utilisé et place le +résultat dans A. En fonction de A les bits de flags sont mis à jour. Utile pour masquer une valeur. +Le ET logique fonctionne comme suit: + A: #10010111b + opérande: #11010010b + ---------- + A: #10010010b + +Le bit de résultat est mis à 1 SI et SEULEMENT SI le bit des deux opérandes sont à 1. + +ASL - Arithmetic Shift Left - +Flags afféctés: N,C,Z +Comme son nom l'indique, cette fonction va effectuer un décalage des bits vers la gauche de l'operande passée +en paramètre et placer le résultat dans cette même opérande. Si le bit 7 de l'opérande est à 1 le bit de retenue +sera mis à 1. + Operande: #10010100b + ---------- + Résultat: #00101000b avec bit de retenue à 1 + _________________ + C<-|7|6|5|4|3|2|1|0|<-0 + ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ + +BCC - Branch if Carry Clear - Instruction de branchement - +Flags afféctés: aucuns +Il s'agit d'une instruction de branchement. Le saut à l'adresse indiquée en paramètre est efféctué si le bit +de retenue (flag C) est à 0 (clear). Le seul mode d'adressage est le mode relatif (voir modes d'adressages). +Si le bit de retenue est à 1, le cycle continue normalement (compteur ordinal incrémenté). + +BCS - Branch if Carry Set - Instruction de branchement - +Flags afféctés: aucuns +Comme la précédente instruction sauf que le branchement s'effectue uniquement si le bit de retenue est à 1, +sinon le programme continue. + +BEQ - Branch if Equal - Instruction de branchement - +Flags afféctés: aucuns +Cette instruction effectue un branchement uniquement si le bit d'etat Zero (Z) est à 1, sinon poursuit sur la +prochaine instruction. Utile pour controler une boucle (souvent avec les registres X et Y). + +BIT - Bit Test - +Flags afféctés: N,V,Z +Effectue un ET logique entre A et l'opérande passée en paramètre (M) et mets le flag à jour mais ne mets pas +le résultat dans A. A ET M est calculé est le resultat est testé. +Exemple: si A ET M = 0 -> flag Z = 1 + +BMI - Branch if Minus - Instruction de branchement - +Flags afféctés: aucuns +Effectue un branchement si le bit d'etat négatif (N) est à 1. Sinon le programme continue sur la prochaine +instruction à executer. + +BNE - Branch if not Equal - Instruction de branchement - +Flags afféctés: aucuns +Effectue un branchement à l'adresse indiquée si le bit d'etat zero (Z) est à 0. Sinon poursuit sur la prochaine +instruction. + +BPL - Branch on Plus - Instruction de branchement - +Flags afféctés: aucuns +Effectue un branchement à l'adresse indiquée si le bit d'etat negatif (N) est à 0. Sinon poursuit sur la prochaine +instruction. + +BRK - Break - +Flags afféctés: B,I +Cette instruction force l'execution d'une interruption IRQ est mets les flags B (Break) et I (Interrupt) à 1. +Les détails sur les interruptions seront évoqués après. + +BVC - Branch if Overflow Clear - +Flags afféctés: aucuns +Effectue un branchement à l'adresse indiquée si le bit de dépassement signé (V) est à 0. Sinon poursuit sur la prochaine +instruction. + +BVS - Branch if Overflow Set - +Flags afféctés: aucuns +Effectue un branchement à l'adresse indiquée si le bit de dépassement signé (V) est à 1. Sinon poursuit sur la prochaine +instruction. + +CLC - Clear Carry - +Flags afféctés: C +Cette instruction remet le bit de retenue du registre d'etat à 0. Indispensable avant de faire un nouveau +calcul à l'aide de l'instruction ADC par exemple. + +CLD - Clear Decimal Mode - +Flags afféctés: D +Cette instruction met le bit du mode décimal (D) à zero. Normalement inutile vu que le processeur commence avec son +registre d'état à 0. + +CLI - Clear Interrupt Disable - +Flags afféctés: I +Cette instruction remet le flag de bloquage des interruptions (I) à 0, autorisant ainsi à nouveau les interruptions. + +CLV - Clear Overflow Flag - +Flags afféctés: V +Cette instruction met le flag d'indication de depassement signé (V) à 0. Indispensable si vous faites des calculs signés +car ils utilisent ce flag. + +CMP - Compare Memory And Accumulateur (comparaison de l'accumulateur avec une valeur en mémoire centrale) - +Flags afféctés: N,Z,C +Il s'agit d'une instruction de comparaison indispensable pour la création de structures conditionelles, pour pouvoir +utiliser ensuite les instructions de branchement. Son fonctionnement est établi comme suit: +Si A < opérande -> N=1, Z=0, C=0 +Si A = opérande -> N=0, Z=1, C=1 +Si A > opérande -> N=0, Z=0, C=1 +Pour définir la valeur de l'opérande on dispose de nombreux modes d'adressage applicables à l'accumulateur. +Cette instruction ne donne pas de résultat mais modifie systématiquement les 3 flags N,Z et C. + +CPX - Compare Memory And X (comparaison du registre X et d'une opérande) - +Flags afféctés: N,Z,C +Pareil que l'instruction précédente mais ici appliqué au registre X, ce qui signifie que beaucoup moins de modes +d'adressages seront disponibles (voir table des opcodes pour détail). + +CPY - Compare Memory And Y (comparaison du registre Y et d'une opérande) - +Flags afféctés: N,Z,C +Même remarque que pour l'instruction précédente. + +DEC - Decrement Source - +Flags afféctés: N,Z +On passe une adresse mémoire d'une opérande, on la décrémente et on place le résultat dans cette même adresse +mémoire. Les flags N et Z seront mis à jour en conséquence (Z si opérande == 0, N si bit 7 de l'opérande est à 1). +Seuls les modes d'adressage absolus sont disponibles pour cette instruction. + +DEX - Decrement X - +Flags afféctés: N,Z +Exactement la même chose que l'instruction précédente, mais ici appliqué au registre X. On n'a donc plus besoin +de passer une adresse à l'instruction. +Remarque interessante: sur cette version du processeur, il n'y pas d'instruction pour incrémenter ou decrémenter +le registre accumulateur! Un oubli qui sera comblé sur le 65C02. + +DEY - Decrement Y - +Flags afféctés: N,Z +Bon est-il vraiment besoin de parler de ca... + +EOR - Exclusive-OR (OU exclusif de la memoire avec l'accumulateur) - +Flags afféctés: N,Z +Encore une instruction logique, un peu plus complexe puisqu'elle correspond a un "( NON (A ET B)) ET (A OU B)" +c'est à dire que vous ne mettez le bit à 1 que si un seul des bits d'origine est à 1, sinon 0. +Voilà comment ca marche: + opérande: #10010110b + A : #11011011b + ---------- + A : #01001101b +En fonction du résultat les flags N et Z seront mis à jour de la même façon que d'habitude. + +INC - Increment Memory - +Flags afféctés: N,Z +Incrémente de 1 l'opérande dont l'adresse est passée en paramètre à l'instruction (définie par le mode d'adressage). +En fonction du résultat les flags N et Z sont mis à jour. + +INX - Increment X - +Flags afféctés: N,Z +Même chose mais pour le registre X. Pas besoin de passer l'adresse c'est une instruction impliée. + +INY - Increment Y - +Flags afféctés: N,Z +Même chose mais pour le registre Y. Pas besoin de passer l'adresse c'est une instruction impliée. + +JMP - Jump - +Flags afféctés: aucuns +Un grand classique, cette instruction effectue un saut inconditionnel direct à l'adresse indiquée dans le programme +et éxecute l'instruction suivante à cette adresse. Elle dispose de 2 modes d'adressage: absolu et, particulier +puisqu'elle est la seule sur le 6502 à l'utiliser, le mode d'adressage indirect absolu +(voir plus haut pour son fonctionnement). + +JSR - Jump to SubRoutine - +Flags afféctés: aucuns +Cette instruction permet de faire un saut vers un sous-code situé dans la suite d'instruction langage machine (PRG-ROM). +L'appel de cette instruction suppose necessairement l'appel prochain de l'instruction RTS ou RTI (voir plus loin). +Alord quelle difference avec l'appel de JMP? Bien cela se situe au niveau de la pile... +Le contenu du registre compteur ordinal (Program Counter) est mis sur la pile à l'appel d'une instruction JSR. +Celui-ci est automatiquement dépilé et restauré à l'appel de RTS. +Comme la plupart du temps on utilise JSR pour simuler le fonctionnement de fonctions, il faudra prévoir +le passage des paramètres. La solution la plus simple consiste a utiliser les registres. +Si vous utilisez la pile faites attention au fait que l'on sauvegarde 16 bits sur la pile à l'appel de JSR et +donc vos paramètres risquent de se retrouver en dessous. +Le seul mode d'adressage disponible pour cette instruction est absolu. + +LDA - Load Accumulator (charger dans l'accumulateur) - +Flags afféctés: N,Z +On passe une adresse en paramètre à l'instruction LDA, l'opérande située à cette adresse en mémoire centrale +est chargée dans l'accumulateur, puis la valeur mise dans l'accumulateur est évaluée pour determiner les flags N et Z. + +LDX - Load Register X (charger dans registre X) - +Flags afféctés: N,Z +La même chose que précedemment, éxcépté le fait que les modes d'adressage indéxé ne peuvent être utilisés. + +LDY - Load Register Y (charger dans registre Y) - +Flags afféctés: N,Z +Pareil qu'avant mais pour le registre Y. + +LSR - Logical Shift Right - +Flags afféctés: N,C,Z +Semblable à l'instruction ASL mais ici le décalage s'effectue vers la droite. On peut soit effectuer le decalage +sur une opérande située en mémoire centrale, soit sur l'accumulateur (A). Si le bit 0 est à 1 avant décalage alors +on met le bit de retenue du registre d'état à 1 (C), sinon à 0. +Exemple: + opérande: #10010101b + --------- + après: : #01001010b avec flag Carry à 1 +En fonction du résultat les bits N et Z seront mis à jour comme d'habitude. + + _________________ + 0->|7|6|5|4|3|2|1|0|->C + ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ + +NOP - No Opération - +Flags afféctés: aucuns +Cette instruction n'effectue rien mais correspond à un cycle complet d'execution d'horloge du processeur, par +conséquent elle est très utile pour ralentir le programme sur une machine dont on sait que la vitesse du processeur +restera constant (c'est le cas de la NES), mais il est plus rigoureux de passer par la méthode du VBlank. + +ORA - Logical Inclusive OR ( OU logique) - +Flags afféctés: N,Z +Cette instruction effectue un OU logique entre l'accumulateur et une opérande située en mémoire centrale. +Le OU a un fonctionnement très simple: si au moins 1 des 2 bits sont à 1, le bit de résultat est à 1. +Voilà comment cela fonctionne en détail: + Accumulateur: #10010100b + opérande : #01001001b + ---------- + Accumulateur: #11011101b +En fonction du résultat dans l'accumulateur, les flags N et Z seront mis à jour. + +PHA - Push A - +Flags afféctés: aucuns +Cette instruction copie l'opérande contenue dans l'accumulateur et l'empile (la place au sommet de la pile). +A chaque opérande empilée bien entendu le pointeur de pile est incrémenté. + +PHP - Push Processor Status Register (empiler le registre d'etat) - +Flags afféctés: aucuns +Cette instruction empile le contenu du registre d'etat. C'est la seule facon d'acceder à son contenu. +C'est très pratique pour executer une suite d'instruction et être sur de pouvoir récupérer son contenu intact +après (à l'aide de l'instruction PLP). + +PLA - Pull Accumulator (dépiler dans l'accumulateur) - +Flags afféctés: N,Z +L'instruction transfert la valeur située au sommet de la pile dans l'accumulateur et +décrémente le pointeur de pile. En fonction de l'opérande placée dans l'accumulateur +les flags N et Z sont mis à jour. + +PLP - Pull Processor Status (dépiler dans le registre d'état) - +Flags afféctés: tous +Cette instruction va dépiler dans le registre d'etat, de fait TOUS les flags seront soumis +à un eventuel changement. + +ROL - Rotate Left (rotation binaire vers la gauche) - +Flags afféctés: N,Z,C +Cette instruction peut sembler identique à ASL mais elle possède une différence fondamentale, en effet le contenu +du bit de retenue est mis au début de l'opérande sur laquelle on effectue un ROL. +Voilà un bref exemple de son fonctionnement: + CLC ; on s'assure que le carry flag est bien à 0 + LDA #10010010b + ROL A ; a ce moment on va avoir dans A la valeur suivante: #00100100b avec notre carry flag à 1 + ROL A ; maintenant le contenu de A est: #01001001b , le carry flag est à 0 +L'opérande passé en paramètre à cette instruction peut être indifférement l'accumulateur ou une opérande +située en mémoire centrale. + _________________ + C<-|7|6|5|4|3|2|1|0|<-C + ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ + +ROR - Rotate Right (rotation binaire vers la droite) - +Flags afféctés: N,Z,C +Son fonctionnement est identique à celui de LSR mais avec les particularités du point de vue de la retenue +énoncées ci-dessus. + _________________ + C->|7|6|5|4|3|2|1|0|->C + ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ +RTI - Return from Interrupt - +Flags afféctés: aucuns +Après l'executation d'une interruption cela permet de restaurer le contenu du compteur ordinal et revenir dans le +programme au moment où l'execution de l'interruption avait commencé. + +RTS - Return from SubRoutine - +Flags afféctés: aucuns +Cette instruction dépile 16 bits pour les mettre dans le registre compteur ordinal (adresse à l'appel de l'instruction JSR) +ce qui provoque un retour à l'endroit d'appel de sous routine dans le programme (PRG-ROM). + +SBC - Substract with Carry - +Flags afféctés: N,Z,C,V +Soustrait de l'accumulateur une opérande dont la valeur se trouve à l'adresse passée en paramètre à l'instruction. +Le résultat est placé dans l'accumulateur est évalué pour déterminer le nouvel état des flags N,Z,C et V. +Attention ne pas oublier la valeur du bit de retenue (flag C). + +SEC - Set Carry Flag - +Flags afféctés: C +Cette instruction met juste le bit de retenue (C) à 1. + +SED - Set Decimal Mode - +Flags afféctés: D +Cette instruction met le bit de mode décimal (D) à 1. + +SEI - Set Interrupt Disable - +Flags afféctés: I +Permet de mettre le flag I (Interrupt Disable) à 1. Cela permet de bloquer les interruptions autres que les NMI +(Non Masquable). + +STA - Store Accumulator - +Flags afféctés: aucuns +Copie le contenu de l'accumulateur à l'adresse en mémoire centrale passée en paramètre à l'instruction. + +STX - Store X Register - +Flags afféctés: aucuns +Pareil que l'instruction précedente mais ici pour le registre X, par conséquent les modes d'adressages indéxés ne peuvent +pas être utilisés. + +STY - Store Y Register - +Flags afféctés: aucuns +Même chose que précédement mais pour le registre Y. + +TAX - Transfer Accumulator to X (transfert l'accumulateur vers registre X) - +Flags afféctés: N,Z +Copie le contenu de l'accumulateur dans X, et mets les flags N et Z à jour en fonction du résultat (normalement inutile). + +TAY - Transfer Accumulator to Y (transfert l'accumulateur vers registre Y) - +Flags afféctés: N,Z +Même chose que précedement mais pour le registre Y. + +TSX - Transfer Stack To X (Mets le contenu du registre pointeur de pile dans le registre X) - +Flags afféctés: N,Z +Mets la valeur du registre pointeur de pile dans le registre X, ce qui permet de savoir sur quelle valeur pointe +actuellement le pointeur de pile. Les flags sont mis à jour en fonction de la valeur dans le registre X. + +TXA - Transfer X to Accumulator - +Flags afféctés: N,Z +Copie la valeur contenue dans le registre X dans l'accumulateur et mets les flags N et Z à jour. + +TXS - Transfer X to Stack - +Flags afféctés: N,Z +Copie le contenu du registre X dans le registre pointeur de pile (S), c'est la seule facon de modifier directement le +pointeur de pile. Cette instruction est notamment utilisée au début d'un programme car le pointeur de pile ne commence +pas automatiquement à l'endroit adéquate ($FF). +On peut également s'en servir pour manipuler la pile plus précisement (passage de paramètre par la pile par exemple). + +TYA - Transfer Y to Accumulator - +Flags afféctés: N,Z +Copie la valeur contenue dans le registre Y dans l'accumulateur et mets les flags N et Z à jour. + + 4. Tableau détaillé des opcodes par ordre alphabetique: + +-------------------------------------------------- + ADC - + Mnemonic Mode d'adressage Opcode Taille + + ADC #aa 69 2 + ADC $aa 65 2 + ADC $aa,X 75 2 + ADC $aaaa 6D 3 + ADC $aaaa,X 7D 3 + ADC $aaaa,Y 79 3 + ADC ($aa,X) 61 2 + ADC ($aa),Y 71 2 + +-------------------------------------------------- + AND - + Mnemonic Mode d'adressage Opcode Taille + + AND #aa 29 2 + AND $aa 25 2 + AND $aa,X 35 2 + AND $aaaa 2D 3 + AND $aaaa,X 3D 3 + AND $aaaa,Y 39 3 + AND ($aa,X) 21 2 + AND ($aa),Y 31 2 + +-------------------------------------------------- + ASL - + Mnemonic Mode d'adressage Opcode Taille + + ASL A 0A 1 + ASL $aa 06 2 + ASL $aa,X 16 2 + ASL $aaaa 0E 3 + ASL $aaaa,X 1E 3 + +-------------------------------------------------- + BCC - + Mnemonic Mode d'adressage Opcode Taille + + BCC $aa 90 2 + +-------------------------------------------------- + BCS - + Mnemonic Mode d'adressage Opcode Taille + + BCS $aa B0 2 + +-------------------------------------------------- + BEQ - + Mnemonic Mode d'adressage Opcode Taille + + BEQ $aa F0 2 + +-------------------------------------------------- + BIT - + Mnemonic Mode d'adressage Opcode Taille + + BIT $aa 24 2 + BIT $aaaa 2C 3 + +-------------------------------------------------- + BMI - + Mnemonic Mode d'adressage Opcode Taille + + BMI $aa 30 2 + +-------------------------------------------------- + BNE - + Mnemonic Mode d'adressage Opcode Taille + + BNE $aa D0 2 + +-------------------------------------------------- + BPL - + Mnemonic Mode d'adressage Opcode Taille + + BPL $aa 10 2 + +-------------------------------------------------- + BRK - + Mnemonic Mode d'adressage Opcode Taille + + BRK 00 1 + +-------------------------------------------------- + BVC - + Mnemonic Mode d'adressage Opcode Taille + + BVC $aa 50 2 + +-------------------------------------------------- + BVS - + Mnemonic Mode d'adressage Opcode Taille + + BVS $aa 70 2 + +-------------------------------------------------- + CLC - + Mnemonic Mode d'adressage Opcode Taille + + CLC 18 1 + +-------------------------------------------------- + CLD - + Mnemonic Mode d'adressage Opcode Taille + + CLD D8 1 + +-------------------------------------------------- + CLI - + Mnemonic Mode d'adressage Opcode Taille + + CLI 58 1 + +-------------------------------------------------- + CLV - + Mnemonic Mode d'adressage Opcode Taille + + CLV B8 1 + +-------------------------------------------------- + CMP - + Mnemonic Mode d'adressage Opcode Taille + + CMP #aa C9 2 + CMP $aa C5 2 + CMP $aa,X D5 2 + CMP $aaaa CD 3 + CMP $aaaa,X DD 3 + CMP $aaaa,Y D9 3 + CMP ($aa,X) C1 2 + CMP ($aa),Y D1 2 + +-------------------------------------------------- + CPX - + Mnemonic Mode d'adressage Opcode Taille + + CPX #aa E0 2 + CPX $aa E4 2 + CPX $aaaa EC 3 + +-------------------------------------------------- + CPY - + Mnemonic Mode d'adressage Opcode Taille + + CPY #aa C0 2 + CPY $aa C4 2 + CPY $aaaa CC 3 + +-------------------------------------------------- + DEC - + Mnemonic Mode d'adressage Opcode Taille + + DEC $aa C6 2 + DEC $aa,X D6 2 + DEC $aaaa CE 3 + DEC $aaaa,X DE 3 + +-------------------------------------------------- + DEX - + Mnemonic Mode d'adressage Opcode Taille + + DEX CA 1 + +-------------------------------------------------- + DEY - + Mnemonic Mode d'adressage Opcode Taille + + DEY 88 1 + +-------------------------------------------------- + EOR - + Mnemonic Mode d'adressage Opcode Taille + + EOR #aa 49 2 + EOR $aa 45 2 + EOR $aa,X 55 2 + EOR $aaaa 4D 3 + EOR $aaaa,X 5D 3 + EOR $aaaa,Y 59 3 + EOR ($aa,X) 41 2 + EOR ($aa),Y 51 2 + +-------------------------------------------------- + INC - + Mnemonic Mode d'adressage Opcode Taille + + INC $aa E6 2 + INC $aa,X F6 2 + INC $aaaa EE 3 + INC $aaaa,X FE 3 + +-------------------------------------------------- + INX - + Mnemonic Mode d'adressage Opcode Taille + + INX E8 1 + +-------------------------------------------------- + INY - + Mnemonic Mode d'adressage Opcode Taille + + INY C8 1 + +-------------------------------------------------- + JMP - + Mnemonic Mode d'adressage Opcode Taille + + JMP $aaaa 4C 3 + JMP ($aaaa) 6C 3 + +-------------------------------------------------- + JSR - + Mnemonic Mode d'adressage Opcode Taille + + JSR $aaaa 20 3 + +-------------------------------------------------- + LDA - + Mnemonic Mode d'adressage Opcode Taille + + LDA #aa A9 2 + LDA $aa A5 2 + LDA $aa,X B5 2 + LDA $aaaa AD 3 + LDA $aaaa,X BD 3 + LDA $aaaa,Y B9 3 + LDA ($aa,X) A1 2 + LDA ($aa),Y B1 2 + +-------------------------------------------------- + LDX - + Mnemonic Mode d'adressage Opcode Taille + + LDX #aa A2 2 + LDX $aa A6 2 + LDX $aa,Y B6 2 + LDX $aaaa AE 3 + LDX $aaaa,Y BE 3 + +-------------------------------------------------- + LDY - + Mnemonic Mode d'adressage Opcode Taille + + LDY #aa A0 2 + LDY $aa A4 2 + LDY $aa,X B4 2 + LDY $aaaa AC 3 + LDY $aaaa,X BC 3 + +-------------------------------------------------- + LSR - + Mnemonic Mode d'adressage Opcode Taille + + LSR A 4A 1 + LSR $aa 46 2 + LSR $aa,X 56 2 + LSR $aaaa 4E 3 + LSR $aaaa,X 5E 3 + +-------------------------------------------------- + NOP - + Mnemonic Mode d'adressage Opcode Taille + + NOP EA 1 + +-------------------------------------------------- + ORA - + Mnemonic Mode d'adressage Opcode Taille + + ORA #aa 09 2 + ORA $aa 05 2 + ORA $aa,X 15 2 + ORA $aaaa 0D 3 + ORA $aaaa,X 1D 3 + ORA $aaaa,Y 19 3 + ORA ($aa,X) 01 2 + ORA ($aa),Y 11 2 + +-------------------------------------------------- + PHA - + Mnemonic Mode d'adressage Opcode Taille + + PHA 48 1 + +-------------------------------------------------- + PHP - + Mnemonic Mode d'adressage Opcode Taille + + PHP 08 1 + +-------------------------------------------------- + PLA - + Mnemonic Mode d'adressage Opcode Taille + + PLA 68 1 + +-------------------------------------------------- + PLP - + Mnemonic Mode d'adressage Opcode Taille + + PLP 28 1 + +-------------------------------------------------- + ROL - + Mnemonic Mode d'adressage Opcode Taille + + ROL A 2A 1 + ROL $aa 26 2 + ROL $aa,X 36 2 + ROL $aaaa 2E 3 + ROL $aaaa,X 3E 3 + +-------------------------------------------------- + ROR - + Mnemonic Mode d'adressage Opcode Taille + + ROR A 6A 1 + ROR $aa 66 2 + ROR $aa,X 76 2 + ROR $aaaa 6E 3 + ROR $aaaa,X 7E 3 + +-------------------------------------------------- + RTI - + Mnemonic Mode d'adressage Opcode Taille + + RTI 40 1 + +-------------------------------------------------- + RTS - + Mnemonic Mode d'adressage Opcode Taille + + RTS 60 1 + +-------------------------------------------------- + SBC - + Mnemonic Mode d'adressage Opcode Taille + + SBC #aa E9 2 + SBC $aa E5 2 + SBC $aa,X F5 2 + SBC $aaaa ED 3 + SBC $aaaa,X FD 3 + SBC $aaaa,Y F9 3 + SBC ($aa,X) E1 2 + SBC ($aa),Y F1 2 + +-------------------------------------------------- + SEC - + Mnemonic Mode d'adressage Opcode Taille + + SEC 38 1 + +-------------------------------------------------- + SED - + Mnemonic Mode d'adressage Opcode Taille + + SED F8 1 + +-------------------------------------------------- + SEI - + Mnemonic Mode d'adressage Opcode Taille + + SEI 78 1 + +-------------------------------------------------- + STA - + Mnemonic Mode d'adressage Opcode Taille + + STA $aa 85 2 + STA $aa,X 95 2 + STA $aaaa 8D 3 + STA $aaaa,X 9D 3 + STA $aaaa,Y 99 3 + STA ($aa,X) 81 2 + STA ($aa),Y 91 2 + +-------------------------------------------------- + STX - + Mnemonic Mode d'adressage Opcode Taille + + STX $aa 86 2 + STX $aa,Y 96 2 + STX $aaaa 8E 3 + +-------------------------------------------------- + STY - + Mnemonic Mode d'adressage Opcode Taille + + STY $aa 84 2 + STY $aa,X 94 2 + STY $aaaa 8C 3 + +-------------------------------------------------- + TAX - + Mnemonic Mode d'adressage Opcode Taille + + TAX AA 1 + +-------------------------------------------------- + TAY - + Mnemonic Mode d'adressage Opcode Taille + + TAY A8 1 + +-------------------------------------------------- + TSX - + Mnemonic Mode d'adressage Opcode Taille + + TSX BA 1 + +-------------------------------------------------- + TXA - + Mnemonic Mode d'adressage Opcode Taille + + TXA 8A 1 + +-------------------------------------------------- + TXS - + Mnemonic Mode d'adressage Opcode Taille + + TXS 9A 1 + +-------------------------------------------------- + TYA - + Mnemonic Mode d'adressage Opcode Taille + + TYA 98 1 + + 5. Interruptions: + +Les interruptions sont des évenements externes au processeur proprement dit qui proviennent des périphériques. +Pour vous donner une idée, lors d'une interruption, le cycle courant des instructions (du programme) est interrompu +quoiqu'il arrive pour executer le code correspondant à l'interruption. +Sur le 6502 il y a 3 type d'interruptions: + +-On distingue d'abord les NMI, Non-Maskable Interrupts. Celles-ci ne peuvent pas être désactivées par l'activation du flag I. +Pour la NES il s'agit surtout des interruptions provenant de la PPU (notamment Vblank). A l'appel de cette interruption +on va éxecuter la sous routine dont l'adresse se trouve dans la mémoire à $FFFA ($FFFA -> low,$FFFB -> high) +La mise à jour d'une NMI est efféctué 60x/secondes(taux de rafraichissement d'un VBlank). +On peut s'en servir pour écrire des données dans la PPU lors d'un VBlank (utilisation la plus couramment constatée). +Ecrire des données en VRAM hors d'un VBlank n'est pas tellement grave sur un émulateur, mais est une source +de bugs inévitable sur la console réelle. + +Les types d'interruptions suivants peuvent être désactivés en mettant le flag I du Processor Status à 1: + +-Il y a ensuite l'interruption RESET, qui est automatiquement éxecutée à la mise en marche du processeur. +L'adresse de la sous-routine de l'interruption RESET est en $FFFC ($FFFC -> low,$FFFD -> high). +Cette interruption etant automatiquement activée au demarrage, l'adresse mise en $FFFC DOIT ABSOLUMENT ETRE LE DEBUT +DU PROGRAMME même si le flag I est activé. + +-Le dernier type d'interruption est soit le fait d'une execution d'une instruction BRK, ou requête d'interruption (IRQ) +de la part d'un périphérique cablé (cette dernière solution n'est pas très importante sur NES et est souvent negligée). +Cépendant l'adresse pour la routine a utiliser est $FFFE. Son utilisation peut notamment être occuré par l'utilisation +du canal sonore DMC, voir détails après. + +Note: il faut impérativement utiliser l'instruction RTI pour terminer une routine qui a été appelée par une interruption! +Note 2: les adresses sont supposées se trouver dans les banques de PRG-ROM, leur emplacement est invariable. + +Avertissement: N'oubliez surtout pas que les interruptions peuvent survenir n'importe quand dans le programme. +Dans vos routines d'interruption, vous allez être amené à modifier le contenu des registres, hors imaginons que +l'interruption arrive au moment où une sous routine est en cours d'execution dans le programme principal par +exemple, le résultat serait que le programme sera faussé par l'execution de la routine de l'interruption. +Pour éviter ce genre de désagrément il suffit de sauvegarder le contenu des registres au debut de l'éxecution +de la routine liée à l'interruption et de le restaurer à la fin. \ No newline at end of file diff --git a/docs/nesdoc2.txt b/docs/nesdoc2.txt new file mode 100644 index 0000000..244fa05 --- /dev/null +++ b/docs/nesdoc2.txt @@ -0,0 +1,865 @@ + +Vous êtes déjà arrivé jusqu'ici?? Wow mes féliciations!! +Maintenant ça risque de devenir un peu plus corsé... + + +Fonctionnement de la PPU (Picture Processing Unit): +-------------------------------------------------- + +Petite intro: + +Comprendre le fonctionnement de la PPU c'est un peu une manière de comprendre +comment une console fonctionne, à savoir décharger le maximum de tâches à +ses coprocesseurs. Dans le cas présent de toute façon la NES a un fonctionnement +extrèmement simple puisque la PPU est le seul véritable coprocesseur. + + 1. Partage de la VRAM: + +La NES dispose de 16 ko de mémoire video (et pas 32 ko comme on peut le voir souvent). +D'ailleurs n'essayez absolument pas de donner au registre d'adresse de la PPU +une adresse sur plus de 14 bits, car les $C000 octets suivants sont juste des +miroirs. +Cette mémoire est complétement dédiée au fonctionnement de la PPU, et n'est pas +directement accessible par le processeur central. Par conséquent, pour pouvoir +accéder à cette mémoire, on dispose de toute une batterie de pseudo-registres qui +sont en fait utilisés tels des adresses en mémoire centrale. Ces pseudo-registres +permettent en fait de piloter la PPU pour l'affichage des sprites, faire des scrollings, +régler les couleurs, ect... + +Voilà comment est partagée la mémoire: +$0 -> $FFF : Table des graphismes #0 (Pattern Table) d'une taille de $1000 (4096) +$1000 -> $1FFF : Table des graphismes #1 d'une taille de $1000 (4096) +-> Remarque: si la rom à un mapper particulier (défini dans l'header), +il y a moyen que ces tables de graphismes soient en fait 2 banques de la rom (CHR-ROM), +ou plus, ce sera expliqué plus loin avec l'utilisation du Multi-Memory Controller. +Quoi qu'il en soit ca n'affectera que les $2000 premiers octets de la VRAM. +$2000 -> $23BF : Table de nommage #0 (Name Table) d'une taille de $3C0 (960) +$23C0 -> $23FF : Table d'attribution #0 (Attribute Table) d'une taille de $40 (64) +$2400 -> $27BF : Table de nommage #1 d'une taille de $3C0 +$27C0 -> $27FF : Table d'attribution #1 d'une taille de $40 +$2800 -> $2BBF : Table de nommage #2 d'une taille de $3C0 +$2BC0 -> $2BFF : Table d'attribution #2 d'une taille de $40 +$2C00 -> $2FBF : Table de nommage #3 d'une taille de $3C0 +$2FC0 -> $2FFF : Table d'attribution #3 d'une taille de $40 +$3000 -> $3EFF : Non utilisé +$3F00 -> $3F0F : Palette des images d'une taille de $10 (16) +$3F10 -> $3F1F : Palette des sprites d'une taille de $10 +$3F20 -> $3FFF : Miroir des palettes d'une taille de $EO (224) + +Au total $4000 octets soit 16384 octets. + +Quelques détails au niveau des miroirs utilisés dans la VRAM: +- les tables de nommage sont soumis à un effet de miroir, qui sera expliqué plus loin. +- même chose pour les palettes. + + 2. Tables des graphismes: + +Il s'agit en fait d'abord d'expliquer comment sont stockées les données graphiques en +mémoire video. Les données sont organisées en "tiles", de 8x8 pixels. +Pour chaque tile les couleurs sont codées sur 2 bits, ainsi pour chaque tile on a +besoin de $10 octets (16). +On se sert des 8 premiers octets pour code le premier bit de chaque pixel et du second +pour le deuxieme bit. Voilà ce que ça donne plus concrètement: + + Premier bit Deuxième bit Représentation de la tile + +1. #00011000b -> $18 9. #10000001b -> $81 2 . . 1 1 . . 2 +2. #01000010b -> $42 10. #00000000b -> $00 . 1 . . . . 1 . +3. #10100101b -> $A5 11. #00100100b -> $24 1 . 3 . . 3 . 1 +4. #10000001b -> $81 12. #00000000b -> $00 1 . . . . . . 1 +5. #01000010b -> $42 13. #00011000b -> $18 . 1 . 2 2 . 1 . +6. #01000010b -> $42 14. #00000000b -> $00 . 1 . . . . 1 . +7. #00111100b -> $3C 15. #00000000b -> $00 . . 1 1 1 1 . . +8. #00000000b -> $00 16. #00011000b -> $18 . . . 2 2 . . . + +Donc la VRAM contient 2 tables des graphismes pouvant chacune contenir 256 tiles (4096 octets). +Soit un total de 512 tiles stockables possibles en mémoire. +Pour pouvoir les afficher on va avoir recours aux tables de nommage. + + 3. Tables de nommage: + +Les tables de nommage sont en fait des matrices de tiles, et vont constituer la base de l'affichage. +La NES a en effet un affichage de 32*30 tiles (soit en pixels 256*240). +Donc 32*30=960 soit la mémoire disponible pour une table de nommage. Chaque octet codé dans la table de nommage +sera un index vers une tile dans la table des graphismes. +Remarque: sur la version NTSC de la NES, les 8 premières et dernières lignes ne sont pas affichées. + + 4. Tables d'attribution: + +Le rôle des tables d'attribution est complémentaire à celui des tables de nommage. +Comme vu précedemment les couleurs des tiles sont codées sur 2 bits. Mais le système de couleur +de la PPU permet un affichage en 16 couleurs, donc codage 4 bits. +Pour pouvoir accéder à ces 16 couleurs on a recours aux tables d'attribution. +Voilà comment ces tables fonctionnent: + +-Chaque octet dans la table d'attribution retient les 2 bits de poids fort de chaque couleur +dans un groupe 4*4 tiles. Pour un groupe de 4 tiles on a ainsi 2 bits dans un octet de la table d'attribution. +On peut controler cette equivalence: +taille de la table d'attribution -> 64 octets +nombre de tiles stockables dans une table de nommage -> 960 + +Cela donne shématiquement: + octet de la table d'attribution #0 + 33221100 + ||||||+--------- tiles #0 à #3 + ||||+----------- tiles #4 à #7 + ||+------------- tiles #8 à #B + +--------------- tiles #C à #F + +Remarque: le numero de tile #? ne correspond pas à l'index de la tile dans la table de nommage + car en réalité les couleurs ne sont pas attribuées séquentiellement mais par blocs de 4 tiles. + + +Complété avec les 2 bits de poids faibles situés dans la table des graphismes on obtient la couleur de la palette qui +sera alors affichée à l'écran. + + 5. Fonctionnement des palettes: + +La PPU utilise 2 palettes : +-la palette des images déstinées à l'affichage des objets statiques d'arrière plan. +-la palette des sprites déstinée comme son nom l'indique à l'affichage des sprites. + +Chacune des palette à une taille de 16 octets. Il ne s'agit pas de réelles valeurs RGB +mais une référence à une palette interne d'une variété de 52 couleurs possibles. +D'autre part les palettes ne sont pas réellement de 16 octets, car les adresses $3F00, +$3F04, $3F08 ect... tous les 4 octets renvois en fait à la même couleur! +Une couleurs très particulière car c'est elle qui va définir la transparence. +Ce qui limite la palette au nombre de couleurs effectif de 13 couleurs +Comme on dispose de 13 couleurs en réalité on peut en afficher jusqu'a 25 (une couleur étant commune aux 2 palettes) +à l'ecran en même temps (fond d'écran + sprites) + +Pour chaque octet de la palette voilà comment proceder: +uullhhhh +|||||||| +||||+----- 4 premiers bits -> défini la valeur chromatique de la couleur: +|||| -> attention cette valeur doit être comprise entre 1 et C (12) (sinon -> couleur noire) +|||| -> mettre 0 permet d'afficher une nuance de gris selon la luminance choisie +||+------- ces 2 bits définissent la luminance, niveau de luminosité choisi ++--------- ces derniers bits ne sont pas utilisés + +Voilà les codes correspondant aux couleurs pour les valeur chromatiques: +$00 = gris $05 = rose $0A = vert +$01 = bleu clair $06 = rouge $0B = vert foncé +$02 = bleu cyan $07 = ocre $0C = bleu ardoise +$03 = bleu foncé $08 = marron +$04 = violet $09 = vert clair +Les niveaux de luminosité peuvent semblibement faire varier ces couleurs +Il existe un très bon tableau pour voir chaque couleur associée à chaque code sur ce site: +http://www.sfu.ca/~ccovell/NESTechFAQ.html + + 6. Fonctionnement des miroirs: + +En réalité la VRAM de la NES dispose d'assez de mémoire pour seulement 2 tables de nommage et 2 tables d'attribution. +Il en résulte que 2 tables sont en fait des "miroirs" des 2 autres tables. +Chaque entrée dans une table est automatiquement alors faites dans l'autre. + +On dispose de 3 modes pour les miroirs (ils sont définis dans l'header pour une rom) : +-le premier mode désactive simplement cet effet, et autorise l'utilisation d'une seule table de nommage (et d'attribution). +-le second mode, le mode "horizontal", permet d'utiliser les tables #0 et #2, la table #1 est un miroir de la table #0 +et la table #3 est un miroir de la table #2. +-le dernier mode, le mode "vertical", permet d'utiliser les tables #0 et #1, la table #2 est un miroir de la table #0 +et la table #3 est un miroir de la table #1. + +Les palettes aussi disposent de miroirs, et chaque intervalle à partir de l'adresse $3F20 jusqu'a $3FFF sont des miroirs +respectifs des 2 palettes tous les $10 octets (16). + + 7. Scrolling de l'arrière plan: + +Comme toute bonne console la NES dispose d'une fonction de scrolling cablée en hardware, ce qui permet un scrolling +irréprochable, contrairement à ce que l'on peut obtenir sur un PC. +Etant donnée qu'une table de nommage équivaut à la taille d'un ecran, il va falloir utiliser la deuxieme table de +nommage à notre disposition. +On peut faire scroller l'arrière plan sur 2 axes seulement: horizontalement et verticalement. +La résolution est de toute facon de 256*240. +Voila shématiquement ce que l'on obtient: + +Horizontal: Vertical: + 0 512 -> 256*2 +---------+0 + +---------+---------+ | | + | | | | A | + | A | B | | | + | | | +---------+ + | | | | | + +---------+---------+ | B | + | | + +---------+480 -> 240*2 + +Pour définir quelle table de nommage on utilise pour "A" on a recours aux bits 0 et 1 du registre $2000 qui sera expliqué +plus loin. Logiquement "B" sera l'autre table de nommage. +Le type de miroir utilisé est défini dans l'header: +Horizontal: Table #0 -> Miroir Table #1 + Table #2 -> Miroir Table #3 +Vertical: Table #0 -> Miroir Table #2 + Table #1 -> Miroir Table #3 + +Le shéma pour le scrolling des tables est le suivant: + + Table de nommage #2 Table de nommage #3 + + + Table de nommage #0 Table de nommage #1 + +L'utilisation du scrolling s'effectue par l'écriture successive de valeurs 8 bits dans le registre $2005. +La première valeur ecrite correspond au scrolling vertical, par conséquent elle doit être impérativement +inférieure ou égale 239 (du fait de la limitation de la résolution de la NES). +La seconde valeur écrite juste après correspond au scrolling horizontal. + + 8. Fonctionnement des sprites: + +La PPU dispose de capacités particulières pour la gestion des sprites. Cela va permettre de simplifier l'affichage +de sprites à l'écran puisqu'ils seront complètement independant de l'arrière plan sur lequel ils vont apparaitre. + +Il y a une mémoire incluse permettant de stocker les informations de 64 sprites, qui peuvent être d'une taille de 8*8 +ou 8*16 pixels (8->largeur, 16->longueur). Les données des sprites sont contenues dans la table des graphismes. +Pour permettre le stockage de ces informations la NES dispose d'un espace mémoire complétement indépendant de la +VRAM et de la mémoire centrale. Cette mémoire est de 256 octets, à raison de 4 octets par sprite (donc capacité pour 64). + +----------------------------------------------------- +Pour un sprite: + -Octet 0 -> Coordonnée Y du point où le sprite se trouve, c'est à dire l'ordonnée. + Ce point est le point du coin haut-gauche du sprite: + + point ->+-------+ + | | + | | + | | + +-------+ + + -Octet 1 -> Il s'agit de l'index dans la table des graphismes des données du sprite. + S'utilise de la même façon que la table de nommage. + Attention les sprites en 8*16 ont une particularité -> voir plus bas. + + -Octet 2 -> Cet octet contient une série de flags qu'il convient d'expliciter: + vhp000cc -> octet divisé par flags + + flag v: Flip Vertical -> mis à 1 active le flip vertical (mouvement rapide), sinon désactivé. + flag h: Flip Horizontal -> même chose horizontalement. + flag p: Priorité d'arrière-plan -> mis à 1 si le sprite doit être caché derrière, sinon laisser à 0. + flag 0: Inutilisé + flag c: Les 2 bits de poids forts de la couleur, car on ne dispose pas ici des tables d'attributions... + Ce flag fonctionne comme les tables d'attribution (voir précédemment). + + -Octet 3 -> Coordonnée X du point où le sprite se trouve, c'est à dire l'abcisse. + +----------------------------------------------------- + +L'utilisation des sprites d'une taille de 8*16 est différente car leur taille fait le double d'une tile normale (8*8). +Par conséquent l'adressage par le biais de l'octet d'index dans une valeur de sprite sera interprété différement +et on accedera ainsi soit à la première table des graphismes (Pattern #0 à l'adresse en VRAM $0000) ou bien +à la seconde table des graphismes (Pattern #1 à l'adresse en VRAM $1000). + +On peut uniquement afficher 8 sprites à la fois sur une "ligne" (scanline), c'est à dire si les sprites ont +les mêmes coordonnées en abcisse(X). Techniquement la PPU peut cependant difficilement gérer plus de sprites que cela. + + 9. VBlank et HBlank: + +VBlank est pour Vertical Blanking, et HBlank pour Horizontal Blanking. Le blanking c'est le scintillement emis par +chaque projection de pixels par le cannon à electrons sur l'écran. La PPU a comme chaque périphérique d'affichage de +console un taux de rafraichissement. Ce taux est de 60 hertz (60x/secondes) pour une NES NTSC et 50 hertz pour une PAL. + +Shématiquement le cannon à élecron va ecrire sur la TV les lignes de gauche à droite et une fois arrivé au bout de +la ligne il doit revenir à gauche pour ecrire la ligne suivante -> cette période est appelée HBlank. + +Une fois tout l'écran complété il doit revenir tout en haut de l'écran pour procéder à l'affichage de l'écran suivant. +Cette période est appelé VBlank. + +On peut voir si la PPU est en période de VBlank en controlant le bit #7 du registre $2002(il est alors à 1), tout comme +on peut mettre celui ci à zero. Celui ci est remis à 0 à la fin du VBlank. + +Le bit #6 du registre $2002 est appelé Hit Flag, et sert a controler à l'affichage d'un sprite quand +est-ce que l'on va ecrire la première ligne du sprite (il sera alors mis à 1). Si la coordonnée en ordonnée (Y) +du sprite est 12, ce flag sera mis à 1 lors de l'écriture de la ligne 12. Il est automatiquement remis à 0 +lors du VBlank. + +On utilise souvent le contrôle du VBlank comme un timer, à défaut d'y avoir une quelquonque horloge sur la NES. + +Fonctionnement des autres peripheriques: +--------------------------------------- + + 1. Pseudo-Audio Processing Unit: + +Comme son nom l'indique la Pseudo-Audio Processing Unit (pAPU) permet à la NES de sortir du son. +Le "Pseudo" vient du fait qu'en réalité il n'existe pas de véritable composant indépendant ayant en charge +le traitement du son (à la différence de la SUPERNES et de son SPC700). +Le son est en fait traité directement par le processeur et une série de composants de base, les synthèses +étant transmises par des registres commandés directement depuis le processeur. + +La NES dispose de 4 voix de synthèses FM et une voix pour le son digital (PCM). +Parmi les voies de synthèses, on compte 2 voix de rythme (pulse), une voix de triangle, et +un canal de bruit. + +Les voix de rythme ont la possibilité de produire du son dans les fréquences de 54,6 Hz à 12,4 Khz. +Il y a possibilité de régler la fréquence de sifflement et la durée du cycle. + +La voix de triangle peut produire du son entre les fréquences 27.3 Hz et 55.9 Khz dans une +résolution de 4-bits (donc 16 tonalitées différentes). Ce canal dispose d'un compteur linéaire +ce qui permet de le désactiver après une certaine période d'utilisation. + +Le canal de bruit lui a la faculté de produire des sons à des fréquences aléatoires entre 29.3 +Hz et 447 KHz. On peut l'utiliser pour produire des nombres aléatoires en sortie du canal (utile +pour les jeux). + +Fonctionnement du canal digital (DMC): +Le canal DMC répond à un fonctionnement bien particulier en comparaison des autres canaux sonores de la pAPU. + + 3. Joypads + +Je ne m'interesserais ici qu'au fonctionnement des 2 joypads de base. Les autres périphériques pourraient +éventuellement être interessants au cas où vous travaillerez sur un émulateur, auquel cas le contenu de +cette documentation se révelerait bien insuffisante. + +La NES supporte donc 2 joypads à la fois (ou un joypad et le Zapper, le pistolet à laser). +Ces 2 joypads correspondent respectivement aux registres $4016 et $4017. Le fonctionnement +des joypads est particulier en comparaison des autres registres de périphérique. +Pour pouvoir utiliser ces registres ont doit d'abord les remettre à l'état initial +en écrivant successivement 1 puis 0 dans le registre adéquate. +Ensuite on doit réalisé le nombre de lecture nécessaire pour accéder à la touche +qui nous interesse de vérifier qu'elle a été préssé. +Nombre de lectures défini comme suit: + +Pour chaque registre (soit $4016 ou $4017): +$4016: + +Joypad #1 Joypad #3 (*) +1 -> A 9 -> A 17 ->----+ +2 -> B 10 -> B 18 -> |___ ces 4 valeurs sont utilisées pour +3 -> SELECT 11 -> SELECT 19 -> | définir quel manette est connectée ("signature") +4 -> START 12 -> START 20 ->----+ +5 -> HAUT 13 -> HAUT 21 -> 0 +6 -> BAS 14 -> BAS 22 -> 0 +7 -> GAUCHE 15 -> GAUCHE 23 -> 0 +8 -> DROITE 16 -> DROITE 24 -> 0 + +* -> le joypad #3 est ici uniquement possible si on utilise l'adaptateur 4 manettes. + Pareil pour le registre $4017, le Joypad #1 équivaut au Joypad #2 + " " " " , le Joypad #3 équivaut au Joypad #4 + Si on utilise pas l'adaptateur 4 manettes les valeurs 9 à 16 sont inutiles. + +Imaginons que nous devions voir si la touche SELECT a été préssée sur le joypad #2, +on aura alors le code assembleur suivant: + +LDA #$01 --| +STA $4017 |---> remise à 0 du port #2 +LDA #$00 --| +STA $4017 +LDA $4017 --| +LDA $4017 |---> 3 lectures pour SELECT +LDA $4017 --| +AND #$01 ------> on ne récupère que le bit #0 (voir details dans "Détails sur les registres de periphériques") + +Si la valeur contenue dans l'accumulateur est à 1 alors la touche SELECT a été cochée. + +Signature: +On peut vérifier en effectuant un certain nombre de lecture (17) +le nombre de joypads connectés. Ainsi on procède comme suit: +%0000 -> aucun joypad ou périphérique connecté +%0001 -> joypad connecté au port #1 ($4016) +#0010 -> joypad connecté au port #2 ($4017) +Remarque: les 4 bits correspondent aux valeurs de 17 à 20. +On obtient cette valeur après 17 lectures dans le registre $4016 ou $4017 + +C'est a peu près tout ce qu'il faut savoir pour les joypads. D'autres types de périphériques d'entrée ont +un fonctionnement légèrement différent cependant ils utilisent quoi qu'il arrive les ports $4016 et $4017. + + +Détails sur les registres de periphériques: +------------------------------------------ + +On a pas directement accès aux périphériques comme la PPU ou bien les joypads, il faut trouver en moyen à partir de la +programmation du processeur central pour piloter ces périphériques. Pour cela on utilise une série de pseudo-registres +qui sont en fait des adresses mémoire. Ces adresses sont données en 16 bits. +Selon le périphérique on va devoir ecrire (cas de la PPU) ou bien lire (généralement pour la pAPU). +On va aussi devoir parfois proceder a une ecriture successive de 2 valeurs. + + + 1. Registres PPU: + + ++--------------------------------------------------------------------------------------------------------+ +|Registre $2000: Registre de contrôle de la PPU #1 (Ecriture seulement) +| masque: vmsbpiNN +| +| v = Mis à 1 ce bit éxecute automatique une routine NMI (Non Maskable Interrupt) lors d'un VBlank +| Rappel: l'adresse de cette routine se trouve en $FFFA dans la PRG-ROM. +| +| m = Selection PPU +| Positionné à Maitre à 0, Esclave à 1. (inutilisé apparament) +| +| s = Taille des sprites +| Si le bit est à 0 -> sprites en 8x8 (taille standard d'une tile) +| " " " -> sprites en 8x16 +| +| b = Adresse de la table des graphismes utilisée pour l'arrière plan en VRAM +| 0 = $0000 +| 1 = $1000 +| +| p = Adresse de la table des graphismes utilisée pour les sprites en VRAM +| 0 = $0000 +| 1 = $1000 +| +| i = Incrémentation d'adresse PPU +| 0 = incrémentation de 1 +| 1 = incrémentation de 32 +| +| NN = Adresse de la table de nommage (Name Table) utilisée en VRAM +| 00 = $2000 +| 01 = $2400 +| 10 = $2800 +| 11 = $2C00 ++--------------------------------------------------------------------------------------------------------+ +|Registre $2001: Registre de contrôle de la PPU (Ecriture seulement) +| masque: fffvVsbt +| +| fff = Couleur de teint utilisée par defaut ("Colour Emphasis") +| 000 = Noir (pas de teint) +| 001 = Rouge +| 010 = Bleu +| 100 = Vert +| Remarque: ce n'est pas encore correctement émulé sur certains émulateurs. +| +| v = Visibilité des sprites (mettre à 1 par défaut pour pouvoir afficher des sprites) +| +| V = Visibilité de l'arrière plan (mettre à 1 par défaut pour pouvoir afficher l'arrière plan) +| +| s = Clipping des sprites +| 0 = les sprites ne sont pas affichés sur les 8 pixels gauches +| 1 = pas de clipping +| +| b = Clipping de l'arrière-plan +| 0 = l'arrière-plan n'est pas affiché sur les 8 pixels gauches +| 1 = pas de clipping +| +| t = Type d'affichage +| 0 = affichage couleur +| 1 = affichage noir et blanc ++--------------------------------------------------------------------------------------------------------+ +|Registre $2002: Registre de Status de la PPU (Lecture seulement) +| masque: vhsw---- (-> 4 bits de poids faibles non utilisés) +| +| v = Période de VBlank +| Ce bit est mis à 1 durant une période de VBlank. +| Il est mis à 0 dès qu'on fait une lecture de ce registre pour +| éviter de reéxecuter une routine dans un même VBlank. +| Remarque: très utile pour s'en servir comme timer. +| +| h = Occurence Sprite #0 +| Ce bit est mis à 1 dès que le VBlank à atteint la position +| du sprite #0 (du moins le premier pixel non transparent). +| Il est mis à 0 après chaque VBlank. +| Voir l'excellente FAQ de Chris Covell pour en savoir d'avantage. +| +| s = Compteur de sprites par ligne +| 0 = 8 ou moins de 8 sprites par ligne +| 1 = plus de 8 sprites par ligne +| +| w = Flag d'ecriture en VRAM +| Ce bit mis à 1 indique que la PPU ignore les ecritures faites en VRAM. +| +| Remarque: Utilisez ce registre SYSTEMATIQUEMENT pour ecrire des données en VRAM. +| Il n'est pas conseillé d'ecrire des données hors d'un VBlank durant l'execution. ++--------------------------------------------------------------------------------------------------------+ +|Registre $2003: Registre d'adresse en SPR-RAM (Ecriture seulement) +| +| Permet d'écrire l'adresse 8 bits utilisée par le registre $2004 +| pour accéder à une case mémoire en SPR-RAM. ++--------------------------------------------------------------------------------------------------------+ +|Registre $2004: Registre d'entrée-sortie en SPR-RAM (Lecture-Ecriture) +| +| Permet d'écrire ou de lire la case d'adresse définie par le registre $2003. ++--------------------------------------------------------------------------------------------------------+ +|Registre $2005: Registre de Scrolling d'arrière-plan (Ecriture seulement) +| +| L'utilisation de ce registre se fait par 2 écritures successives. +| +| 1ère valeur: Scrolling horizontal +| 2ème valeur: Scrolling vertical +| Voir la partie sur les scrollings pour plus d'informations ++--------------------------------------------------------------------------------------------------------+ +|Registre $2006: Registre d'adresse VRAM (Ecriture seulement) +| +| Il s'agit de l'adresse en VRAM que va utiliser le registre $2007. +| L'écriture dans ce registre doit s'effectuer par 2 écritures successives +| étant donné la limitation des bus à 8 bits encore une fois. +| +| 1ère valeur: 8 bits de poids fort de l'adresse +| 2ème valeur: 8 bits de poids faible de l'adresse +| +| REMARQUE: Attention à l'incrémentation d'adresse PPU! A chaque ecriture dans le registre +| $2007, l'adresse du registre $2006 est incrémentée soit de 1 ou de 32 (selon le registre PPU #1) ++--------------------------------------------------------------------------------------------------------+ +|Registre $2007: Registre d'entrée-sortie en VRAM (Lecture-Ecriture) +| +| C'est le registre d'accès à la PPU le plus utilisé. +| C'est par celui ce que vont passer toutes les ecritures pour les tables des graphismes, +| de nommage ou d'attribution, bref toutes les données contenues en VRAM. +| Il s'utilise de paire avec le registre $2006 qui défini l'offset en VRAM. ++--------------------------------------------------------------------------------------------------------+ + + +Gardez à l'esprit que tous les transferts sont efféctués en 8 bits, ce qui inclue de nombreuses boucles si vous +avez des données conséquentes à copier. Ainsi pour la SPR-RAM une autre solution gagne en facilité, expliqué +juste en dessous. + +Registre spécial: +Pour accéder à la SPR-RAM on dispose d'une autre alternative qui facilite grandement les transferts car il +permet de copier un bloc fixe de 256 octets de données qu'on aurait par exemple stocké en RAM ou en PRG-ROM. +Il s'agit d'un registre DMA (Direct Memory Access) semblabe à ceux utilisés pour le son digital. +Ce registre est à l'adresse $4014. +La formule est simple: +$100 * (opérande stockée dans le registre $4014) = adresse de début du bloc de 256 octets ($100) + +Il est conseillé d'utiliser ce registre pour améliorer les performances du programme. + + 2. Registres pAPU + + + + + ++--------------------------------------------------------------------------------------------------------+ +|Registre $4000: Registre de contrôle #1 de la voix de rythme #1 (Ecriture seulement) +| +| masque:%ccvessss +| ||||+---- Taux d'echantillonage en lecture +| |||+----- Selection d'envellope (0 = variée, 1 = fixée) +| ||+------ Vague maintenue: répétion automatique (0 = non, 1 = oui) +| +-------- Accomplissement du cycle +| 00 = 87,5 % +| 00 = 75,0 % +| 00 = 50,0 % +| 00 = 25,0 % ++--------------------------------------------------------------------------------------------------------+ +|Registre $4001: Registre de contrôle #2 de la voix de rythme #1 (Ecriture seulement) +| +| masque:%fsssmrrr +| |||||+--- étalement de la fréquence: 0 est le minimum, 7 le maximum +| ||||| Remarque: voir selon bit #3 pour basse ou haute fréquence +| ||||+---- méthode de fréquence (0 -> de haut vers bas, 1-> de bas vers haut) +| |+------- vitesse de changement de fréquence +| +-------- fréquence de sifflement +| 0 -> les bits #0 à #6 sont ignorés +| 1 -> les bits #0 à #6 sont pris en compte +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4002: Registre de fréquence #1 de la voix de rythme #1 (Ecriture seulement) +| +| Note: la fréquence des voix de rythme sont étalées sur 11 bits. +| Ce registre permet de déterminer la valeur des 8 bits de +| poids faible de la fréquence. +| +| masque:%ffffffff -> 8 bits de poids faible de la fréquence +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4003: Registre de fréquence #2 de la voix de rythme #1 (Ecriture seulement) +| +| masque: %tttttfff +| |||||+--- les 3 bits de poids fort de la fréquence de la voix de rythme #2 +| +-------- temps d'activité de la voix ++--------------------------------------------------------------------------------------------------------+ +|Registre $4004: Registre de contrôle #1 de la voix de rythme #2 (Ecriture seulement) +| +| Son fonctionnement est identique à la voix de rythme #1 (voir registre $4000) +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4005: Registre de contrôle #2 de la voix de rythme #2 (Ecriture seulement) +| +| Son fonctionnement est identique à la voix de rythme #1 (voir registre $4001) +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4006: Registre de fréquence #1 de la voix de rythme #2 (Ecriture seulement) +| +| Son fonctionnement est identique à la voix de rythme #1 (voir registre $4002) +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4007: Registre de fréquence #2 de la voix de rythme #2 (Ecriture seulement) +| +| Son fonctionnement est identique à la voix de rythme #1 (voir registre $4003) +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4008: Registre de contrôle #1 de la voix de triangle (Ecriture seulement) +| +| masque:%vccccccc +| |+------- compteur linéaire de chargement du registre (voir précision précedemment) +| +-------- 0 = longueur d'horloge désactivé +| 1 = démarrage linéaire du compteur ++--------------------------------------------------------------------------------------------------------+ +|Registre $4009: Registre de contrôle #2 de la voix de triangle (Ecriture seulement) +| +| Ce registre n'est pas utilisé. +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $400A: Registre de fréquence #1 de la voix de triangle (Ecriture seulement) +| +| Note: la fréquence de la voix de triangle s'étale sur 11 bits. +| Ce registre permet de déterminer la valeur des 8 bits de +| poids faible de la fréquence. +| +| masque:%ffffffff -> 8 bits de poids faible de la fréquence +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $400B: Registre de fréquence #2 de la voix de triangle (Ecriture seulement) +| +| masque: %tttttfff +| |||||+--- les 3 bits de poids fort de la fréquence de la voix de triangle +| +-------- temps d'activité de la voix ++--------------------------------------------------------------------------------------------------------+ +|Registre $400C: Registre de contrôle #1 du canal de bruit (Ecriture seulement) +| +| masque:%00vessss +| ||||+---- Taux d'echantillonage en lecture +| |||+----- Selection d'envellope (0 = variée, 1 = fixée) +| ||+------ Vague maintenue: répétion automatique (0 = non, 1 = oui) +| +-------- Non utilisés ++--------------------------------------------------------------------------------------------------------+ +|Registre $400D: Registre de contrôle #2 du canal de bruit (Ecriture seulement) +| +| Ce registre n'est pas utilisé. +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $400E: Registre de fréquence #1 du canal de bruit (Ecriture seulement) +| +| Note: la fréquence du canal de bruit s'étale sur 11 bits. +| Ce registre permet de déterminer la valeur des 8 bits de +| poids faible de la fréquence. +| +| masque:%ffffffff -> 8 bits de poids faible de la fréquence +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $400F: Registre de fréquence #2 du canal de bruit (Ecriture seulement) +| +| masque: %tttttfff +| |||||+--- les 3 bits de poids fort de la fréquence du canal de bruit +| +-------- temps d'activité de la voix ++--------------------------------------------------------------------------------------------------------+ +|Registre $4010: Registre de contrôle du canal de son digital (DMC) (Ecriture seulement) +| +| masque:%i???ssss +| ||||+---- fréquence d'échantillonage utilisée +| |+------- fonction inconnue +| +-------- génére une interruption de type IRQ à l'execution (peut être masquée) +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4011: Registre du volume du canal de son digital DMC (Ecriture seulement) +| +| Les 8 bits sont utilisés pour définir le volume du canal. +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4012: Registre d'adresse des données digitales du canal DMC (Ecriture seulement) +| +| Ces 8 bits détermine l'endroit où on doit lire les données pour +| le canal DMC. +| Les données seront lues dans la 2ème banque de PRG-ROM, c'est à dire de $C000 à $FFFF. +| La formule pour trouver l'adresse est la suivante: +| ((valeur 8 bits stockée dans $4012) * 64) + $C000 +| Rappel: 64 = $40 +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4013: Registre de longueur des données digitales (Ecriture seulement) +| +| Définit la longueur de l'échantillon digital à lire à l'adresse $4012 +| La formule pour calculer sa taille est: +| ((valeur 8 bits stockée dans $4013) * 16) + 1 +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4014: Registre d'accès direct à la mémoire (DMA) SPR-RAM (Ecriture seulement) +| +| Voir PPU - Registre spécial. +| ++--------------------------------------------------------------------------------------------------------+ +|Registre $4015: Registre d'état de la PPU (Lecture-Ecriture) +| +| En lecture, ce registre à seulement une fonction: +| Seul le bit #0 est important, si il est à 1 c'est que la PPU est en cours d'utilisation +| +| En écriture: +| masque:%000edcba +| |||||||+- voix de rythme #1 (0 = désactivée, 1 = activée) +| ||||||+-- voix de rythme #2 (0 = désactivée, 1 = activée) +| |||||+--- voix de triangle (0 = désactivée, 1 = activée) +| ||||+---- canal de bruit (0 = désactivée, 1 = activée) +| |||+----- canal digital (0 = désactivée, 1 = activée) +| +-------- bits non utilisés +| +| ++--------------------------------------------------------------------------------------------------------+ + +Les registres de contrôle des canaux sonores servent juste à configurer les canaux (généralement ceci est fait +une seule fois avant de jouer la chanson). Les "notes" sont envoyées par le biais des registres de fréquences +avec la fréquence utilisée ainsi que la durée. +Le mieux que je puisse vous conseiller c'est de tester ces canaux et d'essayer d'implémenter des partitions +récupérées dans des fichiers NSF. Il existe de nombreuses documentations qui expliquent comment procéder. Il +existe également un logiciel sur le site NES Development permettant facilement d'écrire une musique et de +l'implémenter ensuite dans une rom. + + + 3. Registres Joypads + + ++--------------------------------------------------------------------------------------------------------+ +|Registre $4016: Registre de contrôle du Joypad #1 (Lecture-Ecriture) +| +| En lecture: +| %???zteed +| |||||||+----- donnée du joypad (voir détails périphériques) +| |||||+------- lire des données du port d'expansion (utilisé par certains périphériques) +| ||||+-------- indique la gachette du Zapper a été préssée +| |||+--------- indique qu'un sprite se trouve devant le viseur du Zapper +| +------------ utilisation inconnue +| +| En écriture: +| %?????ees +| |||||||+----- Mise à jour état des touches du joypad (nécessaire pour lecture des touches) +| ||||||| 0 = efface l'état +| ||||||| 1 = reset l'état +| ||||||| Voir détails précedemment. +| |||||+------- écriture de données dans le port d'expansion +| +------------ utisation inconnue ++--------------------------------------------------------------------------------------------------------+ +|Registre $4017: Registre de contrôle du Joypad #2 (Lecture-Ecriture) +| +| Son fonctionnement est identique à celui du registre précedent. +| ++--------------------------------------------------------------------------------------------------------+ + + +Autres choses utiles: +-------------------- + + 1. Structure iNes: + +Ici ne sera abordé que la structure iNes, qui utilise un header de 16 octets des fichiers .NES. +Cet header ne fait pas vraiment parti de la rom mais contient des informations indispensables +à son fonctionnement pour un emulateur (notamment si on utilise un mapper particulier). +C'est un standart de fait et il existe d'autres formats (voir meilleurs). + +L'header iNes est de 16 octets($10): + +Adresse |Taille |Contenu + | | +0 |3 |Contient les 3 caractères ASCII 'NES' + | | +3 |1 |Contient la valeur $1A + | | +4 |1 |Nombre de pages de PRG-ROM de 16 ko dans la rom + | | +5 |1 |Nombre de pages de CHR-ROM de 8 ko dans la rom + | | +6 |1 |Octet de controle de la ROM #1: + | |masque: %mmmmvtsm + | | |||||||+-- Miroir utilisé en VRAM (0=horizontal,1=vertical) + | | ||||||+--- utilisation de SRAM ou non pour les sauvegardes (1=oui) + | | |||||+---- presence d'un trainer de 512 octets + | | ||||+----- Possibilité d'utiliser 4 Name Table indépendantes en VRAM + | | +--------- 4 bits de poids faible du mapper utilisé + | | +7 |1 |Octet de controle de la ROM #2: + | |masque: %mmmm0000 + | | ||||+------ ces 4 bits sont toujours à 0 + | | +---------- 4 bits de poids faible du mapper utilisé + | | + | | + | |Remarque: les octets suivants sont ignorés par la plupart des émulateurs et doivent rester à 0 +--------------------------------------------------------------------------------------------------------------- + +Normalement il est d'usage de faire suivre le code (PRG-ROM) juste après l'header. +Les pages CHR-ROM suivront donc logiquement et seront automatiquement chargées dans +les tables des graphismes. L'utilisation de la CHR-ROM annihile toute possibilité +d'écrire dans la VRAM de $0000 à $2000 sous peine de provoquer une erreur de bus, +cette mémoire étant dorénavant considérée comme en disponible en lecture seule. +On peut ne mettre le code qu'en utilisant que la deuxième page également. +Si vous utilisez +de 2 page de PRG-ROM et +de 2 pages de CHR-ROM il vous +faudra utiliser un mapper. +Si vous n'utilisez qu'une page de PRG-ROM il s'agit toujours de la page commençant en $C000. + + 2. Multi-Memory Controler: + +L'utilisation du Multi-Memory Controller est indispensable pour obtenir une taille de rom >40 ko. +Son utilisation va de paire avec ce que l'on appele un mapper. Le mapper utilisé est défini dans l'header. +Son support par les émulateurs fut longtemps un problème. Il n'y aura pas beaucoup de détails sur cette +partie car la mémoire disponible en standard par une rom est largement suffisante pour une démo. + +Tous les mappers sont détaillés à cette adresse: + +http://free.prohosting.com/~nintendo/mappers.nfo + + +Détails sur les méthodes d'assemblage: +------------------------------------- + +La NES est une machine très ancienne et relativement limitée, néanmoins en assembleur il est possible de tirer d'une +machine de nombreuses ressources puisque l'on travaille directement avec le matériel. +Mais il convient alors t'integrer des méthodes de programmation particulières, ainsi que d'autres propres +au système proprement dit. + +Il ne faut surtout pas hésiter à ménager la mémoire disponible en utilisant abondamment le masquage de bit pour les +valeurs ne nécéssitant pas beaucoup de combinaisons. C'est à dire utiliser un octet pour définir sur des plages de +bits (flags) des valeurs. + + On peut procéder ainsi: + +Si le monstre reponds masque suivant: + ____________ + | | | | + bbbb bbb b + | | +---- bit de vérification d'activation du monstre + | +------- flag de 3 bits pour la vie du monstre + +----------- flag de 4 bits pour le type de monstre + + ;on veut coder un monstre + ;le nombre maximum de point de vie possible pour un monstre dans mon jeu est 3 + ;il y a 15 monstres différents et on doit aussi avoir une valeur pour voir si il est actif ou non + LDA monstre_1 + AND #$F0 + LSR A + LSR A + LSR A + LSR A + PHA + JSR type_monstre ;routine pour identifier le monstre + LDA monstre_1 + AND #$0E + LSR A + PHA + JSR degats_monstre + + + +Sur NES notamment, on ne dispose pas d'horloge intégré comme sur un micro-ordinateur (du moins à partir de 1990 la plupart +en ont été équipé). Par contre pour palier à ce défaut, on peut utiliser le signal VBlank cablé en hardware répondant +à partir d'un registre particulier et d'un routine d'interruption. +Deux moyens répondant toutes deux à des besoins différents. Il faut savoir que sur la NES réelle écrire en mémoire vidéo +hors que lors du déroulement du VBlank est une source de bug innérante. Par conséquent on est obligé de s'imposer une +certaine rigueur de programmation. Rigueur qui n'est pas obligatoirement reproductible lorsque l'on n'a comme seul moyen +de test un émulateur. + +Il existe 2 moyens pour utiliser le VBlank: +-soit activer le bit #7 du registre $2000 de la PPU pour generer automatique une interruption non masquable et donc +appeler la sous routine d'adresse définie par le vecteur situé en $FFFA. Ceci fait vous pouvez placer absolument tout +le code que vous voulez du moment que ca n'excede pas la durée du VBlank en éxecution qui est d'environ 16 millisecondes. +Ca suffit normalement pour placer une quantité de code relativement suffisante. +Il faut bien réaliser que cette routine sera éxécuté 60x par seconde (pour une machine NTSC, par défaut sur la plupart +des émulateurs). + +-l'autre moyen c'est de controler lorsqu'un VBlank survient par le biais du bit #7 du registre $2002. Il suffit de créer +une routine qui boucle indéfinimment tant que cette condition n'est pas satisfaite. Normalement cela ne pose pas de problème. +Attention si vous utilisez également les NMI ainsi que cette méthode car la NMI sera toujours satisfaite d'abord et +ensuite uniquement votre routine sera éxecuté. +En outre après la lecture du registre $2002 le bit #7 sera automatiquement remis à 0. Un détail qui a une importance +majeure puisqu'il va éviter de réexecuter une seconde fois la routine, ce qui fausserait complétement le programme. + + + +Epilogue: +-------- + +Je tiens à remercier tous les auteurs des documentations déjà disponibles en anglais, notamment Y0shi, Chris Covell +dont la plupart de ce document à été constitué, ainsi que la plupart des auteurs de documentations disponibles +sur l'excellent site NES Development: http://nesdev.parodius.com. +Sans eux rien n'aurait été possible. +Je tiens également à remercier ceux qui vont utiliser et distribuer ce document, et j'encourage vivement ce type +d'initiatives. J'éspère sincérement qu'il vous sera utile autant qu'il m'a été agréable de l'écrire. + +Détails et remarques: crispysix@wanadoo.fr + +------------------------- c'est ------------------ terminé --------------------------- + diff --git a/osx/English.lproj/InfoPlist.strings b/osx/English.lproj/InfoPlist.strings new file mode 100755 index 0000000..354a827 Binary files /dev/null and b/osx/English.lproj/InfoPlist.strings differ diff --git a/osx/English.lproj/SDLMain.nib/classes.nib b/osx/English.lproj/SDLMain.nib/classes.nib new file mode 100644 index 0000000..799eaad --- /dev/null +++ b/osx/English.lproj/SDLMain.nib/classes.nib @@ -0,0 +1,19 @@ +{ + IBClasses = ( + {CLASS = FirstResponder; LANGUAGE = ObjC; SUPERCLASS = NSObject; }, + { + ACTIONS = { + help = id; + newGame = id; + openGame = id; + prefsMenu = id; + saveGame = id; + saveGameAs = id; + }; + CLASS = SDLMain; + LANGUAGE = ObjC; + SUPERCLASS = NSObject; + } + ); + IBVersion = 1; +} \ No newline at end of file diff --git a/osx/English.lproj/SDLMain.nib/info.nib b/osx/English.lproj/SDLMain.nib/info.nib new file mode 100644 index 0000000..1d6fb7e --- /dev/null +++ b/osx/English.lproj/SDLMain.nib/info.nib @@ -0,0 +1,21 @@ + + + + + IBDocumentLocation + 62 117 356 240 0 0 1152 848 + IBEditorPositions + + 29 + 62 362 195 44 0 0 1152 848 + + IBFramework Version + 291.0 + IBOpenObjects + + 29 + + IBSystem Version + 6L60 + + diff --git a/osx/English.lproj/SDLMain.nib/objects.nib b/osx/English.lproj/SDLMain.nib/objects.nib new file mode 100644 index 0000000..6378015 Binary files /dev/null and b/osx/English.lproj/SDLMain.nib/objects.nib differ diff --git a/osx/Info.plist b/osx/Info.plist new file mode 100644 index 0000000..569b6d2 --- /dev/null +++ b/osx/Info.plist @@ -0,0 +1,28 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleExecutable + ${EXECUTABLE_NAME} + CFBundleIconFile + + CFBundleIdentifier + com.yourcompany.nes + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + ${PRODUCT_NAME} + CFBundlePackageType + APPL + CFBundleSignature + ???? + CFBundleVersion + 1.0 + NSMainNibFile + SDLMain + NSPrincipalClass + NSApplication + + diff --git a/osx/SDLMain.h b/osx/SDLMain.h new file mode 100644 index 0000000..d18cac7 --- /dev/null +++ b/osx/SDLMain.h @@ -0,0 +1,17 @@ +/* SDLMain.m - main entry point for our Cocoa-ized SDL app + Initial Version: Darrell Walisser + Non-NIB-Code & other changes: Max Horn + + Feel free to customize this file to suit your needs +*/ + +#import + +@interface SDLMain : NSObject +- (IBAction)prefsMenu:(id)sender; +- (IBAction)newGame:(id)sender; +- (IBAction)openGame:(id)sender; +- (IBAction)saveGame:(id)sender; +- (IBAction)saveGameAs:(id)sender; +- (IBAction)help:(id)sender; +@end diff --git a/osx/SDLMain.m b/osx/SDLMain.m new file mode 100644 index 0000000..b1007e3 --- /dev/null +++ b/osx/SDLMain.m @@ -0,0 +1,436 @@ +/* SDLMain.m - main entry point for our Cocoa-ized SDL app + Initial Version: Darrell Walisser + Non-NIB-Code & other changes: Max Horn + + Feel free to customize this file to suit your needs +*/ + +#import "SDL.h" +#import "SDLMain.h" +#import /* for MAXPATHLEN */ +#import + +/* For some reaon, Apple removed setAppleMenu from the headers in 10.4, + but the method still is there and works. To avoid warnings, we declare + it ourselves here. */ +@interface NSApplication(SDL_Missing_Methods) +- (void)setAppleMenu:(NSMenu *)menu; +@end + +/* Use this flag to determine whether we use SDLMain.nib or not */ +#define SDL_USE_NIB_FILE 1 + +/* Use this flag to determine whether we use CPS (docking) or not */ +#define SDL_USE_CPS 1 +#ifdef SDL_USE_CPS +/* Portions of CPS.h */ +typedef struct CPSProcessSerNum +{ + UInt32 lo; + UInt32 hi; +} CPSProcessSerNum; + +extern OSErr CPSGetCurrentProcess( CPSProcessSerNum *psn); +extern OSErr CPSEnableForegroundOperation( CPSProcessSerNum *psn, UInt32 _arg2, UInt32 _arg3, UInt32 _arg4, UInt32 _arg5); +extern OSErr CPSSetFrontProcess( CPSProcessSerNum *psn); + +#endif /* SDL_USE_CPS */ + +static int gArgc; +static char **gArgv; +static BOOL gFinderLaunch; +static BOOL gCalledAppMainline = FALSE; + +static NSString *getApplicationName(void) +{ + NSDictionary *dict; + NSString *appName = 0; + + /* Determine the application name */ + dict = (NSDictionary *)CFBundleGetInfoDictionary(CFBundleGetMainBundle()); + if (dict) + appName = [dict objectForKey: @"CFBundleName"]; + + if (![appName length]) + appName = [[NSProcessInfo processInfo] processName]; + + return appName; +} + +#if SDL_USE_NIB_FILE +/* A helper category for NSString */ +@interface NSString (ReplaceSubString) +- (NSString *)stringByReplacingRange:(NSRange)aRange with:(NSString *)aString; +@end +#endif + +@interface SDLApplication : NSApplication +@end + +@implementation SDLApplication +/* Invoked from the Quit menu item */ +- (void)terminate:(id)sender +{ + /* Post a SDL_QUIT event */ + SDL_Event event; + event.type = SDL_QUIT; + SDL_PushEvent(&event); +} +@end + +/* The main class of the application, the application's delegate */ +@implementation SDLMain + +- (IBAction)prefsMenu:(id)sender +{ + printf ("prefs menu\n"); +} + +- (IBAction)newGame:(id)sender +{ + printf ("new game\n"); + + NSRunAlertPanel (@"Get ready to blow up some... stuff!", + @"Click OK to begin total carnage. Click Cancel to prevent total carnage.", @"OK", @"Cancel", nil); +} + +- (IBAction)openGame:(id)sender +{ + NSString *path = nil; + NSOpenPanel *openPanel = [ NSOpenPanel openPanel ]; + + if ( [ openPanel runModalForDirectory:nil + file:@"SavedGame" types:nil ] ) { + + path = [ [ openPanel filenames ] objectAtIndex:0 ]; + } + + printf ("open game: %s\n", [ path cString ]); +} + +- (IBAction)saveGame:(id)sender +{ + NSString *path = nil; + NSSavePanel *savePanel = [ NSSavePanel savePanel ]; + + if ( [ savePanel runModalForDirectory:nil + file:@"SaveGameFile" ] ) { + + path = [ savePanel filename ]; + } + + printf ("save game: %s\n", [ path cString ]); +} + +- (IBAction)saveGameAs:(id)sender +{ + printf ("save game as\n"); +} + +- (IBAction)help:(id)sender +{ + NSRunAlertPanel (@"Oh help, where have ye gone?", + @"Sorry, there is no help available.\n\nThis message brought to you by We Don't Document, Inc.\n\n", @"Rats", @"Good, I never read it anyway", nil); +} + + +/* Set the working directory to the .app's parent directory */ +- (void) setupWorkingDirectory:(BOOL)shouldChdir +{ + if (shouldChdir) + { + char parentdir[MAXPATHLEN]; + CFURLRef url = CFBundleCopyBundleURL(CFBundleGetMainBundle()); + CFURLRef url2 = CFURLCreateCopyDeletingLastPathComponent(0, url); + if (CFURLGetFileSystemRepresentation(url2, true, (UInt8 *)parentdir, MAXPATHLEN)) { + assert ( chdir (parentdir) == 0 ); /* chdir to the binary app's parent */ + } + CFRelease(url); + CFRelease(url2); + } + +} + +#if SDL_USE_NIB_FILE + +/* Fix menu to contain the real app name instead of "SDL App" */ +- (void)fixMenu:(NSMenu *)aMenu withAppName:(NSString *)appName +{ + NSRange aRange; + NSEnumerator *enumerator; + NSMenuItem *menuItem; + + aRange = [[aMenu title] rangeOfString:@"SDL App"]; + if (aRange.length != 0) + [aMenu setTitle: [[aMenu title] stringByReplacingRange:aRange with:appName]]; + + enumerator = [[aMenu itemArray] objectEnumerator]; + while ((menuItem = [enumerator nextObject])) + { + aRange = [[menuItem title] rangeOfString:@"SDL App"]; + if (aRange.length != 0) + [menuItem setTitle: [[menuItem title] stringByReplacingRange:aRange with:appName]]; + if ([menuItem hasSubmenu]) + [self fixMenu:[menuItem submenu] withAppName:appName]; + } + [ aMenu sizeToFit ]; +} + +#else + +static void setApplicationMenu(void) +{ + /* warning: this code is very odd */ + NSMenu *appleMenu; + NSMenuItem *menuItem; + NSString *title; + NSString *appName; + + appName = getApplicationName(); + appleMenu = [[NSMenu alloc] initWithTitle:@""]; + + /* Add menu items */ + title = [@"About " stringByAppendingString:appName]; + [appleMenu addItemWithTitle:title action:@selector(orderFrontStandardAboutPanel:) keyEquivalent:@""]; + + [appleMenu addItem:[NSMenuItem separatorItem]]; + + title = [@"Hide " stringByAppendingString:appName]; + [appleMenu addItemWithTitle:title action:@selector(hide:) keyEquivalent:@"h"]; + + menuItem = (NSMenuItem *)[appleMenu addItemWithTitle:@"Hide Others" action:@selector(hideOtherApplications:) keyEquivalent:@"h"]; + [menuItem setKeyEquivalentModifierMask:(NSAlternateKeyMask|NSCommandKeyMask)]; + + [appleMenu addItemWithTitle:@"Show All" action:@selector(unhideAllApplications:) keyEquivalent:@""]; + + [appleMenu addItem:[NSMenuItem separatorItem]]; + + title = [@"Quit " stringByAppendingString:appName]; + [appleMenu addItemWithTitle:title action:@selector(terminate:) keyEquivalent:@"q"]; + + + /* Put menu into the menubar */ + menuItem = [[NSMenuItem alloc] initWithTitle:@"" action:nil keyEquivalent:@""]; + [menuItem setSubmenu:appleMenu]; + [[NSApp mainMenu] addItem:menuItem]; + + /* Tell the application object that this is now the application menu */ + [NSApp setAppleMenu:appleMenu]; + + /* Finally give up our references to the objects */ + [appleMenu release]; + [menuItem release]; +} + +/* Create a window menu */ +static void setupWindowMenu(void) +{ + NSMenu *windowMenu; + NSMenuItem *windowMenuItem; + NSMenuItem *menuItem; + + windowMenu = [[NSMenu alloc] initWithTitle:@"Window"]; + + /* "Minimize" item */ + menuItem = [[NSMenuItem alloc] initWithTitle:@"Minimize" action:@selector(performMiniaturize:) keyEquivalent:@"m"]; + [windowMenu addItem:menuItem]; + [menuItem release]; + + /* Put menu into the menubar */ + windowMenuItem = [[NSMenuItem alloc] initWithTitle:@"Window" action:nil keyEquivalent:@""]; + [windowMenuItem setSubmenu:windowMenu]; + [[NSApp mainMenu] addItem:windowMenuItem]; + + /* Tell the application object that this is now the window menu */ + [NSApp setWindowsMenu:windowMenu]; + + /* Finally give up our references to the objects */ + [windowMenu release]; + [windowMenuItem release]; +} + +/* Replacement for NSApplicationMain */ +static void CustomApplicationMain (int argc, char **argv) +{ + NSAutoreleasePool *pool = [[NSAutoreleasePool alloc] init]; + SDLMain *sdlMain; + + /* Ensure the application object is initialised */ + [SDLApplication sharedApplication]; + +#ifdef SDL_USE_CPS + { + CPSProcessSerNum PSN; + /* Tell the dock about us */ + if (!CPSGetCurrentProcess(&PSN)) + if (!CPSEnableForegroundOperation(&PSN,0x03,0x3C,0x2C,0x1103)) + if (!CPSSetFrontProcess(&PSN)) + [SDLApplication sharedApplication]; + } +#endif /* SDL_USE_CPS */ + + /* Set up the menubar */ + [NSApp setMainMenu:[[NSMenu alloc] init]]; + setApplicationMenu(); + setupWindowMenu(); + + /* Create SDLMain and make it the app delegate */ + sdlMain = [[SDLMain alloc] init]; + [NSApp setDelegate:sdlMain]; + + /* Start the main event loop */ + [NSApp run]; + + [sdlMain release]; + [pool release]; +} + +#endif + + +/* + * Catch document open requests...this lets us notice files when the app + * was launched by double-clicking a document, or when a document was + * dragged/dropped on the app's icon. You need to have a + * CFBundleDocumentsType section in your Info.plist to get this message, + * apparently. + * + * Files are added to gArgv, so to the app, they'll look like command line + * arguments. Previously, apps launched from the finder had nothing but + * an argv[0]. + * + * This message may be received multiple times to open several docs on launch. + * + * This message is ignored once the app's mainline has been called. + */ +- (BOOL)application:(NSApplication *)theApplication openFile:(NSString *)filename +{ + const char *temparg; + size_t arglen; + char *arg; + char **newargv; + + if (!gFinderLaunch) /* MacOS is passing command line args. */ + return FALSE; + + if (gCalledAppMainline) /* app has started, ignore this document. */ + return FALSE; + + temparg = [filename UTF8String]; + arglen = SDL_strlen(temparg) + 1; + arg = (char *) SDL_malloc(arglen); + if (arg == NULL) + return FALSE; + + newargv = (char **) realloc(gArgv, sizeof (char *) * (gArgc + 2)); + if (newargv == NULL) + { + SDL_free(arg); + return FALSE; + } + gArgv = newargv; + + SDL_strlcpy(arg, temparg, arglen); + gArgv[gArgc++] = arg; + gArgv[gArgc] = NULL; + return TRUE; +} + + +/* Called when the internal event loop has just started running */ +- (void) applicationDidFinishLaunching: (NSNotification *) note +{ + int status; + + /* Set the working directory to the .app's parent directory */ + [self setupWorkingDirectory:gFinderLaunch]; + +#if SDL_USE_NIB_FILE + /* Set the main menu to contain the real app name instead of "SDL App" */ + [self fixMenu:[NSApp mainMenu] withAppName:getApplicationName()]; +#endif + + /* Hand off to main application code */ + gCalledAppMainline = TRUE; + status = SDL_main (gArgc, gArgv); + + /* We're done, thank you for playing */ + exit(status); +} +@end + + +@implementation NSString (ReplaceSubString) + +- (NSString *)stringByReplacingRange:(NSRange)aRange with:(NSString *)aString +{ + unsigned int bufferSize; + unsigned int selfLen = [self length]; + unsigned int aStringLen = [aString length]; + unichar *buffer; + NSRange localRange; + NSString *result; + + bufferSize = selfLen + aStringLen - aRange.length; + buffer = NSAllocateMemoryPages(bufferSize*sizeof(unichar)); + + /* Get first part into buffer */ + localRange.location = 0; + localRange.length = aRange.location; + [self getCharacters:buffer range:localRange]; + + /* Get middle part into buffer */ + localRange.location = 0; + localRange.length = aStringLen; + [aString getCharacters:(buffer+aRange.location) range:localRange]; + + /* Get last part into buffer */ + localRange.location = aRange.location + aRange.length; + localRange.length = selfLen - localRange.location; + [self getCharacters:(buffer+aRange.location+aStringLen) range:localRange]; + + /* Build output string */ + result = [NSString stringWithCharacters:buffer length:bufferSize]; + + NSDeallocateMemoryPages(buffer, bufferSize); + + return result; +} + +@end + + + +#ifdef main +# undef main +#endif + + +/* Main entry point to executable - should *not* be SDL_main! */ +int main (int argc, char **argv) +{ + /* Copy the arguments into a global variable */ + /* This is passed if we are launched by double-clicking */ + if ( argc >= 2 && strncmp (argv[1], "-psn", 4) == 0 ) { + gArgv = (char **) SDL_malloc(sizeof (char *) * 2); + gArgv[0] = argv[0]; + gArgv[1] = NULL; + gArgc = 1; + gFinderLaunch = YES; + } else { + int i; + gArgc = argc; + gArgv = (char **) SDL_malloc(sizeof (char *) * (argc+1)); + for (i = 0; i <= argc; i++) + gArgv[i] = argv[i]; + gFinderLaunch = NO; + } + +#if SDL_USE_NIB_FILE + [SDLApplication poseAsClass:[NSApplication class]]; + NSApplicationMain (argc, argv); +#else + CustomApplicationMain (argc, argv); +#endif + return 0; +} diff --git a/osx/nes.xcodeproj/jbnadal.mode1v3 b/osx/nes.xcodeproj/jbnadal.mode1v3 new file mode 100644 index 0000000..e95abe0 --- /dev/null +++ b/osx/nes.xcodeproj/jbnadal.mode1v3 @@ -0,0 +1,1383 @@ + + + + + ActivePerspectiveName + Project + AllowedModules + + + BundleLoadPath + + MaxInstances + n + Module + PBXSmartGroupTreeModule + Name + Groups and Files Outline View + + + BundleLoadPath + + MaxInstances + n + Module + PBXNavigatorGroup + Name + Editor + + + BundleLoadPath + + MaxInstances + n + Module + XCTaskListModule + Name + Task List + + + BundleLoadPath + + MaxInstances + n + Module + XCDetailModule + Name + File and Smart Group Detail Viewer + + + BundleLoadPath + + MaxInstances + 1 + Module + PBXBuildResultsModule + Name + Detailed Build Results Viewer + + + BundleLoadPath + + MaxInstances + 1 + Module + PBXProjectFindModule + Name + Project Batch Find Tool + + + BundleLoadPath + + MaxInstances + n + Module + XCProjectFormatConflictsModule + Name + Project Format Conflicts List + + + BundleLoadPath + + MaxInstances + n + Module + PBXBookmarksModule + Name + Bookmarks Tool + + + BundleLoadPath + + MaxInstances + n + Module + PBXClassBrowserModule + Name + Class Browser + + + BundleLoadPath + + MaxInstances + n + Module + PBXCVSModule + Name + Source Code Control Tool + + + BundleLoadPath + + MaxInstances + n + Module + PBXDebugBreakpointsModule + Name + Debug Breakpoints Tool + + + BundleLoadPath + + MaxInstances + n + Module + XCDockableInspector + Name + Inspector + + + BundleLoadPath + + MaxInstances + n + Module + PBXOpenQuicklyModule + Name + Open Quickly Tool + + + BundleLoadPath + + MaxInstances + 1 + Module + PBXDebugSessionModule + Name + Debugger + + + BundleLoadPath + + MaxInstances + 1 + Module + PBXDebugCLIModule + Name + Debug Console + + + BundleLoadPath + + MaxInstances + n + Module + XCSnapshotModule + Name + Snapshots Tool + + + BundlePath + /Developer/Library/PrivateFrameworks/DevToolsInterface.framework/Resources + Description + DefaultDescriptionKey + DockingSystemVisible + + Extension + mode1v3 + FavBarConfig + + PBXProjectModuleGUID + EF7231D50D6EFD890032A59D + XCBarModuleItemNames + + XCBarModuleItems + + + FirstTimeWindowDisplayed + + Identifier + com.apple.perspectives.project.mode1v3 + MajorVersion + 33 + MinorVersion + 0 + Name + Default + Notifications + + OpenEditors + + PerspectiveWidths + + -1 + -1 + + Perspectives + + + ChosenToolbarItems + + active-target-popup + active-buildstyle-popup + action + NSToolbarFlexibleSpaceItem + buildOrClean + build-and-goOrGo + com.apple.ide.PBXToolbarStopButton + get-info + toggle-editor + NSToolbarFlexibleSpaceItem + com.apple.pbx.toolbar.searchfield + + ControllerClassBaseName + + IconName + WindowOfProjectWithEditor + Identifier + perspective.project + IsVertical + + Layout + + + BecomeActive + + ContentConfiguration + + PBXBottomSmartGroupGIDs + + 1C37FBAC04509CD000000102 + 1C37FAAC04509CD000000102 + 1C08E77C0454961000C914BD + 1C37FABC05509CD000000102 + 1C37FABC05539CD112110102 + E2644B35053B69B200211256 + 1C37FABC04509CD000100104 + 1CC0EA4004350EF90044410B + 1CC0EA4004350EF90041110B + + PBXProjectModuleGUID + 1CE0B1FE06471DED0097A5F4 + PBXProjectModuleLabel + Files + PBXProjectStructureProvided + yes + PBXSmartGroupTreeModuleColumnData + + PBXSmartGroupTreeModuleColumnWidthsKey + + 186 + + PBXSmartGroupTreeModuleColumnsKey_v4 + + MainColumn + + + PBXSmartGroupTreeModuleOutlineStateKey_v7 + + PBXSmartGroupTreeModuleOutlineStateExpansionKey + + 29B97314FDCFA39411CA2CEA + 29B97315FDCFA39411CA2CEA + EF7231AD0D6EFD080032A59D + EF7231B40D6EFD080032A59D + 1C37FAAC04509CD000000102 + 1C37FABC05509CD000000102 + + PBXSmartGroupTreeModuleOutlineStateSelectionKey + + + 4 + 3 + 2 + 0 + + + PBXSmartGroupTreeModuleOutlineStateVisibleRectKey + {{0, 23}, {186, 338}} + + PBXTopSmartGroupGIDs + + XCIncludePerspectivesSwitch + + XCSharingToken + com.apple.Xcode.GFSharingToken + + GeometryConfiguration + + Frame + {{0, 0}, {203, 356}} + GroupTreeTableConfiguration + + MainColumn + 186 + + RubberWindowFrame + 37 432 690 397 0 0 1280 832 + + Module + PBXSmartGroupTreeModule + Proportion + 203pt + + + Dock + + + ContentConfiguration + + PBXProjectModuleGUID + 1CE0B20306471E060097A5F4 + PBXProjectModuleLabel + MyNewFile14.java + PBXSplitModuleInNavigatorKey + + Split0 + + PBXProjectModuleGUID + 1CE0B20406471E060097A5F4 + PBXProjectModuleLabel + MyNewFile14.java + + SplitCount + 1 + + StatusBarVisibility + + + GeometryConfiguration + + Frame + {{0, 0}, {482, 0}} + RubberWindowFrame + 37 432 690 397 0 0 1280 832 + + Module + PBXNavigatorGroup + Proportion + 0pt + + + ContentConfiguration + + PBXProjectModuleGUID + 1CE0B20506471E060097A5F4 + PBXProjectModuleLabel + Detail + + GeometryConfiguration + + Frame + {{0, 5}, {482, 351}} + RubberWindowFrame + 37 432 690 397 0 0 1280 832 + + Module + XCDetailModule + Proportion + 351pt + + + Proportion + 482pt + + + Name + Project + ServiceClasses + + XCModuleDock + PBXSmartGroupTreeModule + XCModuleDock + PBXNavigatorGroup + XCDetailModule + + TableOfContents + + EF6096DC0DA3CED100A4D4F1 + 1CE0B1FE06471DED0097A5F4 + EF6096DD0DA3CED100A4D4F1 + 1CE0B20306471E060097A5F4 + 1CE0B20506471E060097A5F4 + + ToolbarConfiguration + xcode.toolbar.config.defaultV3 + + + ControllerClassBaseName + + IconName + WindowOfProject + Identifier + perspective.morph + IsVertical + 0 + Layout + + + BecomeActive + 1 + ContentConfiguration + + PBXBottomSmartGroupGIDs + + 1C37FBAC04509CD000000102 + 1C37FAAC04509CD000000102 + 1C08E77C0454961000C914BD + 1C37FABC05509CD000000102 + 1C37FABC05539CD112110102 + E2644B35053B69B200211256 + 1C37FABC04509CD000100104 + 1CC0EA4004350EF90044410B + 1CC0EA4004350EF90041110B + + PBXProjectModuleGUID + 11E0B1FE06471DED0097A5F4 + PBXProjectModuleLabel + Files + PBXProjectStructureProvided + yes + PBXSmartGroupTreeModuleColumnData + + PBXSmartGroupTreeModuleColumnWidthsKey + + 186 + + PBXSmartGroupTreeModuleColumnsKey_v4 + + MainColumn + + + PBXSmartGroupTreeModuleOutlineStateKey_v7 + + PBXSmartGroupTreeModuleOutlineStateExpansionKey + + 29B97314FDCFA39411CA2CEA + 1C37FABC05509CD000000102 + + PBXSmartGroupTreeModuleOutlineStateSelectionKey + + + 0 + + + PBXSmartGroupTreeModuleOutlineStateVisibleRectKey + {{0, 0}, {186, 337}} + + PBXTopSmartGroupGIDs + + XCIncludePerspectivesSwitch + 1 + XCSharingToken + com.apple.Xcode.GFSharingToken + + GeometryConfiguration + + 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/dev/null +++ b/src/cpu/cpu6502.c @@ -0,0 +1,3071 @@ +/*---------------------------------------------------------------------------- + * cpu 6502.c: Main file CPU 6502 (NES CPU) Emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include +#include + +#include "opcodes.h" +#include "cpu6502.h" + +#include "debug.h" + +/* TODO Remove this trace. */ +# define PRINT_OP(a) + +/******************************************************* + * Push the parameter on the stack. + */ +void Push (nes_cpu6502_t *cpu, uint8_t value) +{ + cpu->memWrite (STACK_END + cpu->R_Stack, value); + DEBUG2 (("Push a %x = %x\n", cpu->R_Stack, value)); + cpu->R_Stack--; +} + +/******************************************************* + * Pop the parameter from the stack. + */ +uint8_t Pop (nes_cpu6502_t *cpu) +{ + cpu->R_Stack++; + return cpu->memRead (STACK_END + cpu->R_Stack); +} + +/******************************************************* + * This function reset the target Machine. + */ +int cpuReset (nes_cpu6502_t *cpu) +{ + int result = 0; + + /* Reset the CPU. */ + cpu->a = 0; + cpu->x = 0; + cpu->y = 0; + cpu->R_Status = 0; + cpu->R_Stack = STACK_START; + + /* Set the PC. */ + /* -Low part. */ + cpu->pc = cpu->memRead (0xFFFC); + /* -Hight part. */ + cpu->pc |= cpu->memRead (0xFFFD) << 8; + + return result; +} + +/******************************************************* + * This function Launch an nmi. + */ +void NMI_Interrupt (nes_cpu6502_t *cpu) +{ + uint8_t param8_1, param8_2; + + param8_1 = cpu->memRead (0x2000); + + if (param8_1 & 0x80) { + + /*Push PC. */ + param8_1 = (cpu->pc & 0xFF00) >> 8; + param8_2 = (cpu->pc & 0xFF); + + Push (cpu, param8_1); + Push (cpu, param8_2); + /* Push Status. */ + Push (cpu, cpu->R_Status); + + /* Jump to NMI function. */ + DEBUG0 (("switch to NMI.\n")); + /* Set the PC. */ + /* -Low part. */ + cpu->pc = cpu->memRead (0xFFFA); + /* -Hight part. */ + cpu->pc |= cpu->memRead (0xFFFB) << 8; + + /* The nmi switch take 7 cycles. */ + cpu->nbCycles -= 7; + } +} + +/******************************************************* + * Set a value to the register A. + */ +void SetA (nes_cpu6502_t *cpu, uint8_t val) +{ + cpu->a = val; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.a == cpu->a) { + fprintf (stdout, "cpu.alert.a = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Decrement the Value of the register A. + */ +void DecA (nes_cpu6502_t *cpu) +{ + cpu->a--; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.a == cpu->a) { + fprintf (stdout, "cpu.alert.a = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Increment the Value of the register A. + */ +void IncA (nes_cpu6502_t *cpu) +{ + cpu->a++; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.a == cpu->a) { + fprintf (stdout, "cpu.alert.a = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Set a value to the register X. +*/ +void SetX (nes_cpu6502_t *cpu, uint8_t val) +{ + cpu->x = val; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.x == cpu->x) { + fprintf (stdout, "cpu.alert.x = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Decrement the Value of the register X. + */ +void DecX (nes_cpu6502_t *cpu) +{ + cpu->x--; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.x == cpu->x) { + fprintf (stdout, "cpu.alert.x = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Increment the Value of the register X. + */ +void IncX (nes_cpu6502_t *cpu) +{ + cpu->x++; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.x == cpu->x) { + fprintf (stdout, "cpu.alert.x = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Set a value to the register Y. + */ +void SetY (nes_cpu6502_t *cpu, uint8_t val) +{ + cpu->y = val; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.y == cpu->y) { + fprintf (stdout, "cpu.alert.y = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Decrement the Value of the register Y. + */ +void DecY (nes_cpu6502_t *cpu) +{ + cpu->y--; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.y == cpu->y) { + fprintf (stdout, "cpu.alert.y = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Increment the Value of the register Y. + */ +void IncY (nes_cpu6502_t *cpu) +{ + cpu->y++; + + if (cpu->alert.active == 1) { + /* Debugger Mode, we check if an alert is set on this + * register, and if the value correspond to the alert. */ + if (cpu->alert.y == cpu->y) { + fprintf (stdout, "cpu.alert.y = val\n"); + debugger_stop (); + } + } +} + +/******************************************************* + * Init the CPU. +*/ +void bitset (uint8_t *reg, uint8_t flag, uint8_t val) +{ + if (val == 0) { + *reg &= ~(1 << flag); + } + else { + *reg |= (1 << flag); + } +} + +/******************************************************* + * This function used to DEBUG to show the registers. +*/ +void printRegs (nes_cpu6502_t *cpu) +{ + char buffer[11]; + + sprintf (buffer, "[........]"); + if (((cpu->R_Status >> STATUS_FLAG_N) & 0x1) == 1) + buffer[1] = 'N'; + if (((cpu->R_Status >> STATUS_FLAG_V) & 0x1) == 1) + buffer[2] = 'V'; + if (((cpu->R_Status >> STATUS_FLAG_B) & 0x1) == 1) + buffer[4] = 'B'; + if (((cpu->R_Status >> STATUS_FLAG_D) & 0x1) == 1) + buffer[5] = 'D'; + if (((cpu->R_Status >> STATUS_FLAG_I) & 0x1) == 1) + buffer[6] = 'I'; + if (((cpu->R_Status >> STATUS_FLAG_Z) & 0x1) == 1) + buffer[7] = 'Z'; + if (((cpu->R_Status >> STATUS_FLAG_C) & 0x1) == 1) + buffer[8] = 'C'; + + fprintf (stdout, "A:%2.2x X:%2.2x Y:%2.2x S:%4.4x, PC:%4.4x Flags:%s," + " Stack[%2.2x, %2.2x, %2.2x]\n", + cpu->a, cpu->x, cpu->y, cpu->R_Stack + 0x100, + cpu->pc, buffer, + cpu->memRead (STACK_END + (uint8_t)(cpu->R_Stack+1)), + cpu->memRead (STACK_END + (uint8_t)(cpu->R_Stack+2)), + cpu->memRead (STACK_END + (uint8_t)(cpu->R_Stack+3))); +#if 0 + fprintf (stdout, "A:%2.2x X:%2.2x Y:%2.2x S:%4.4x, PC:%4.4x Flags:%s," + " Stack[%2.2x, %2.2x, %2.2x], %.3d, %.3d\n", + emul.cpu.a, emul.cpu.x, emul.cpu.y, emul.cpu.R_Stack + 0x100, + emul.cpu.pc, buffer, + emul.memory.segment1 [STACK_END + (uint8_t)(emul.cpu.R_Stack+1)], + emul.memory.segment1 [STACK_END + (uint8_t)(emul.cpu.R_Stack+2)], + emul.memory.segment1 [STACK_END + (uint8_t)(emul.cpu.R_Stack+3)], + emul.nbCycles, emul.nbLines); +#endif +} + +/******************************************************* + * Init the CPU. +*/ +int cpu6502_init (nes_cpu6502_t *cpu) +{ + int result = 0; + + return result; +} + +/******************************************************* + * Update Flag N and Z of the Status. +*/ +void UpdateFlagsN_Z (nes_cpu6502_t *cpu, uint8_t reg) +{ + uint8_t val; + /* Update Flag N. */ + if (reg & 0x80) { + DEBUG2 (("val 1 donc %x est negatif\n", reg)); + val = 1; + } + else { + DEBUG2 (("val 0 donc %x est positif\n", reg)); + val = 0; + } + /* And update. */ + bitset (&cpu->R_Status, STATUS_FLAG_N, val); + + /* Update Flag Z. */ + if (reg == 0) { + val = 1; + } + else { + val = 0; + } + + /* And update. */ + bitset (&cpu->R_Status, STATUS_FLAG_Z, val); + + DEBUG2 (("Update FlagN et Z-Done (%d)\n", cpu->R_Status)); +} + +/******************************************************* + * Update Flag C of the Status. +*/ +void UpdateFlagsC_L (nes_cpu6502_t *cpu, uint8_t reg) +{ + if (reg & 0x80) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } +} + +/*******************************************************/ +void UpdateFlagsC_R (nes_cpu6502_t *cpu, uint8_t reg) +{ + if (reg & 0x01) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } +} + + +/******************************************************* + * Update Flag I of the Status. +*/ +void UpdateFlagsI (nes_cpu6502_t *cpu, uint8_t value) +{ + bitset (&cpu->R_Status, STATUS_FLAG_I, value); + DEBUG2 (("Update FlagI-Done (%d)\n", cpu->R_Status)); +} + +/******************************************************* + * Update Flag D of the Status. +*/ +void UpdateFlagsD (nes_cpu6502_t *cpu, uint8_t value) +{ + bitset (&cpu->R_Status, STATUS_FLAG_D, value); + DEBUG2 (("Update FlagD-Done (%d)\n", cpu->R_Status)); +} + +/******************************************************* + * Make a Jump to the specified address if the status + * bit N is equal to 0. OtherWise go to the next instruction. + */ +void BranchOnPlus (nes_cpu6502_t *cpu, int8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_N) & 0x1) == 0) { + DEBUG2 (("On doit brancher\n a :%x(%d)\n", + cpu->pc + (int8_t)index, index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher N vaut 1\n")); + } +} + +/******************************************************* + * Make a Jump to the specified address if the status + * bit N is equal to 1. OtherWise go to the next instruction. + */ +void BranchIfMinus (nes_cpu6502_t *cpu, int8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_N) & 0x1) == 1) { + DEBUG2 (("On doit brancher\n a :%x(%d)\n", + cpu->pc + (int8_t)index, index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher N vaut 0\n")); + } +} + +/******************************************************* + * Compare A and the Operande and save the result in the + * Status flags like that: + * + * If A < opérande -> N=1, Z=0, C=0 + * If A = opérande -> N=0, Z=1, C=1 + * If A > opérande -> N=0, Z=0, C=1 + */ +void CompareReg (nes_cpu6502_t *cpu, uint8_t regValue, uint8_t operande) +{ + DEBUG2 (("Compare %d et %d\n", regValue, operande)); + int16_t result; + + /* Substract the two operande to make know the result of the compare. */ + result = regValue - operande; + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, result); + + /* Update Carry status. */ + if (result & 0xff00) { + /* Carry Set. */ + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the Carry is set. + * + */ +void BranchIfCarrySet (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_C) & 0x1) == 1) { + DEBUG2 (("Carry is set, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher C vaut 0\n")); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the Carry is clear. + * + */ +void BranchIfCarryClear (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_C) & 0x1) == 0) { + DEBUG2 (("Carry is set, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher C vaut 1\n")); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the Overflow + * flag is clear. + */ +void BranchIfOverflowClear (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_V) & 0x1) == 0) { + DEBUG2 (("Overflow is Clear, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher V vaut 1\n")); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the Overflow is set. + * + */ +void BranchIfOverflowSet (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_V) & 0x1) == 1) { + DEBUG2 (("Overflow is set, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher V vaut 0\n")); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the + * Zero status is equal to 0. + */ +void BranchIfNotEqual (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_Z) & 0x1) == 0) { + DEBUG2 (("status Zero = 0, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } + else { + DEBUG2 (("Pas la peine de brancher Z vaut 1\n")); + } +} + +/******************************************************* + * Branch to the Address given as parameter if the + * Zero status is equal to 1. + */ +void BranchIfEqual (nes_cpu6502_t *cpu, uint8_t index) +{ + if (((cpu->R_Status >> STATUS_FLAG_Z) & 0x1) == 1) { + DEBUG2 (("status Zero = 1, Jump to :%x\n", + cpu->pc + (int8_t)index)); + cpu->pc += (int8_t)index; + cpu->nbCycles--; + } +} + + +/******************************************************* + * Add with Carry. + */ +void AddWithCarry (nes_cpu6502_t *cpu, uint8_t operande) +{ + uint16_t value; + uint8_t value2, value3; + + value = cpu->a + operande + (cpu->R_Status & FLAG_C); + value2 = cpu->a ^ operande; + + /* Update Carry status. */ + if (value & 0xff00) { + /* Carry Set. */ + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Update V */ + value2 = ~value2; + value3 = cpu->a ^ (value & 0xFF); + + /* Overflow */ + bitset (&cpu->R_Status, STATUS_FLAG_V, ((value2 & value3) & 0x80)>>7); + + /* Update the register. */ + SetA (cpu, value & 0xff); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); +} + +/******************************************************* + * Substract with Carry. + */ +void SubstractWithCarry (nes_cpu6502_t *cpu, uint8_t operande) +{ + uint16_t value; + uint8_t value2, value3; + + value = cpu->a - operande - (~cpu->R_Status & (1 << STATUS_FLAG_C)); + value2 = cpu->a ^ operande; + + DEBUG2 (("value = a(%x) - (%x) - (%x)\n", + cpu->a, operande, (~cpu->R_Status & (1 << STATUS_FLAG_C)))); + + /* Update Carry status. */ + if (value & 0xff00) { + /* Carry Set. */ + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + + /* Update V */ + value3 = cpu->a ^ (value & 0xFF); + + /* Overflow */ + bitset (&cpu->R_Status, STATUS_FLAG_V, ((value2 & value3) & 0x80)>>7); + + /* Update the register. */ + SetA (cpu, value & 0xff); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); +} + + +/******************************************************* + * Make a Logical AND test between the data at the adress + * given as parameter and the A register. + * + * Affected Flags: N,V,Z + */ +void Bit_Test (nes_cpu6502_t *cpu, uint16_t addr) +{ + uint8_t RegValue = cpu->memRead (addr); + + DEBUG2 (("BITest: %d & %d \n", cpu->a, value)); + + /* Update Z */ + if ((cpu->a & RegValue) == 0) { + bitset (&cpu->R_Status, STATUS_FLAG_Z, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_Z, 0); + } + /* Update N */ + if (RegValue & 0x80) { + /* Negative */ + bitset (&cpu->R_Status, STATUS_FLAG_N, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_N, 0); + } + /* Update V */ + if (RegValue & 0x40) { + /* Overflow */ + bitset (&cpu->R_Status, STATUS_FLAG_V, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_V, 0); + } +} + +/******************************************************* + * Execute the OpCode. +*/ +int cpu6502_execOpCode (nes_cpu6502_t *cpu, uint8_t opcode) +{ + int result = 0; + uint16_t param16, param16_2, value; + uint8_t param8_1, param8_2, param8_3, tmp; + + switch (opcode) { + case OP_CODE_BRK: + /* 0x00 - Break. Soft Interrupt. */ + if (((cpu->R_Status >> STATUS_FLAG_I) & 0x1) == 0) { + + /*Push PC. */ + param8_1 = (cpu->pc & 0xFF00) >> 8; + param8_2 = (cpu->pc & 0xFF); + + Push (cpu, param8_1); + Push (cpu, param8_2); + + /* Push Status. */ + Push (cpu, cpu->R_Status|B_FLAG); + + /* Jump to NMI function. */ + DEBUG0 (("switch to NMI.\n")); + /* -Low part. */ + cpu->pc = cpu->memRead (0xFFFF); + /* -Hight part. */ + cpu->pc |= cpu->memRead (0xFFFE) << 8; + } + PRINT_OP (("AT PC: [%.2x - BRK]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_SEI: + /* 0x78 - SEI - Set Interrupt disable. */ + UpdateFlagsI (cpu, 1); + PRINT_OP (("AT PC: [%.2x - SEI]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_SED: + /* 0xf8 - SED - Set Decimal Mode. */ + bitset (&cpu->R_Status, STATUS_FLAG_D, 1); + PRINT_OP (("AT PC: [%.2x - SED]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_SEC: + /* 0x38 - SEC - Set Carry Flag. */ + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + PRINT_OP (("AT PC: [%.2x - SEC]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_CLC: + /* 0x18 - CLC - Clear Carry. */ + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + PRINT_OP (("AT PC: [%.2x - CLC]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_CLD: + /* 0xd8 - Clear Decimal Mode. */ + UpdateFlagsD (cpu, 0); + PRINT_OP (("AT PC: [%.2x - CLD]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_CLV: + /* 0xb8 - Clear Overflow Flag. */ + bitset (&cpu->R_Status, STATUS_FLAG_V, 0); + PRINT_OP (("AT PC: [%.2x - CLV]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_LDA_1: + /* 0xa9 - LDA #aa */ + SetA (cpu, cpu->memRead (++cpu->pc)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA #$%.2x]\n", opcode, cpu->a)); + cpu->pc++; + break; + case OP_CODE_LDA_2: + /* 0xa5 - LDA $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + SetA (cpu, cpu->memRead (param8_1)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDA_3: + /* 0xb5 - LDA $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + SetA (cpu, cpu->memRead ((cpu->x + param8_1) & 0xFF)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDA_4: + /* 0xad - LDA $aaaa */ + + /* Read 16 bits Parameter. */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + SetA (cpu, cpu->memRead (param16)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDA_5: + /* 0xbd - LDA $aaaa, X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + SetA (cpu, cpu->memRead (cpu->x + param16)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDA_6: + /* 0xb9 - LDA $aaaa, Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + SetA (cpu, cpu->memRead (cpu->y + param16)); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDA_7: + /* 0xa1 - LDA ($aa,X) */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + SetA (cpu, cpu->memRead (param16)); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDA_8: + /* 0xb1 - LDA ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + SetA (cpu, cpu->memRead (param16 + cpu->y)); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - LDA ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDX_1: + /* 0xa2 - LDX #aa */ + + SetX (cpu, cpu->memRead (++cpu->pc)); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - LDX #$%.2x]\n", opcode, cpu->x)); + cpu->pc++; + break; + case OP_CODE_LDX_2: + /* 0xa6 - LDX $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + SetX (cpu, cpu->memRead (param8_1)); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - LDX $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDX_3: + /* 0xb6 - LDX $aa,Y */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + SetX (cpu, cpu->memRead ((param8_1 + cpu->y) & 0xFF)); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - LDX $%.2x,Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDX_4: + /* 0xae - LDX $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the value. */ + SetX (cpu, cpu->memRead (param16)); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - LDX $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDX_5: + /* 0xbe - LDX $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + SetX (cpu, cpu->memRead (param16 + cpu->y)); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - LDX $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDY_1: + /* 0xa0 - LDY #aa */ + + SetY (cpu, cpu->memRead (++cpu->pc)); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - LDY #$%.2x]\n", opcode, cpu->y)); + cpu->pc++; + break; + case OP_CODE_LDY_2: + /* 0xa4 - LDY $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + SetY (cpu, cpu->memRead (param8_1)); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - LDY $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDY_3: + /* 0xb4 - LDY $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Add the Value of Reg Y. */ + param8_2 = (param8_1 + cpu->x) & 0xFF; + + /* Read Value. */ + SetY (cpu, cpu->memRead (param8_2)); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - LDY $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LDY_4: + /* 0xac - LDY $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the value. */ + SetY (cpu, cpu->memRead (param16)); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - LDY $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LDY_5: + /* 0xbc - LDY $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the value. */ + SetY (cpu, cpu->memRead (param16 + cpu->x)); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - LDY $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_STA_1: + /* 0x85 - STA $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + cpu->memWrite (param8_1, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STA_2: + /* 0x95 - STA $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Add the Register X. */ + param8_2 = (param8_1 + cpu->x) & 0xFF; + + cpu->memWrite (param8_2, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STA_3: + /* 0x8d - STA $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + cpu->memWrite (param16, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_STA_4: + /* 0x9d - STA $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + cpu->memWrite (param16 + cpu->x, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_STA_5: + /* 0x99 - STA $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + cpu->memWrite (param16 + cpu->y, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_STA_6: + /* 0x81 - LDA ($aa,X) */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + cpu->memWrite (param16, cpu->a); + + PRINT_OP (("AT PC: [%.2x - STA ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STA_7: + /* 0x91 - STA ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + cpu->memWrite (param16 + cpu->y, cpu->a); + PRINT_OP (("AT PC: [%.2x - STA ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STX_1: + /* 0x86 - STX $aa */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + cpu->memWrite (param8_1, cpu->x); + PRINT_OP (("AT PC: [%.2x - STX $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STX_2: + /* 0x96 - STX $aa,Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + cpu->memWrite ((param8_1 + cpu->y) & 0xFF, cpu->x); + PRINT_OP (("AT PC: [%.2x - STX $%.2x,Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STX_3: + /* 0x8e - STX $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + cpu->memWrite (param16, cpu->x); + PRINT_OP (("AT PC: [%.2x - STX $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_STY_1: + /* 0x84 - STY $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + cpu->memWrite (param8_1, cpu->y); + PRINT_OP (("AT PC: [%.2x - STY $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STY_2: + /* 0x94 - STY $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, cpu->y); + PRINT_OP (("AT PC: [%.2x - STY $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_STY_3: + /* 0x8c - STY $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + cpu->memWrite (param16, cpu->y); + PRINT_OP (("AT PC: [%.2x - STY $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_TXS: + /* 0x9a - Transfert X to Stack. */ + + cpu->R_Stack = cpu->x; + + PRINT_OP (("AT PC: [%.2x - TXS]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_TXA: + /* 0x8a - TXA - Transfer X to Register A */ + + SetA (cpu, cpu->x); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - TXA]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_TAX: + /* 0xaa - TAX - Transfer Accumulator to X */ + + SetX (cpu, cpu->a); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - TAX]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_TYA: + /* 0x98 - TYA - Transfer Y to Register A */ + + SetA (cpu, cpu->y); + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - TYA]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_TAY: + /* 0xa8 - TAY - Transfer Accumulator to Y */ + + SetY (cpu, cpu->a); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - TAY]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_TSX: + /* 0xba - TSX - Transfer Stack To X */ + + SetX (cpu, cpu->R_Stack); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - TSX]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_BPL: + /* 0x10 - BPL - Branch on Plus */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BPL $%.2x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchOnPlus (cpu, param8_1); + break; + case OP_CODE_BMI: + /* 0x30 - BMI - Branch if Minus */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BMI $%x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfMinus (cpu, param8_1); + break; + case OP_CODE_CMP_1: + /* 0xc9 - CMP #aa */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + CompareReg (cpu, cpu->a, param8_1); + PRINT_OP (("AT PC: [%.2x - CMP #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CMP_2: + /* 0xc5 - CMP $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_2); + PRINT_OP (("AT PC: [%.2x - CMP $%x]\n", opcode, param8_1)); + cpu-> pc++; + break; + case OP_CODE_CMP_3: + /* 0xd5 - CMP $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_2); + PRINT_OP (("AT PC: [%.2x - CMP $%x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CMP_4: + /* 0xcd - CMP $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_1); + PRINT_OP (("AT PC: [%.2x - CMP $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_CMP_5: + /* 0xdd - CMP $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_1); + PRINT_OP (("AT PC: [%.2x - CMP $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_CMP_6: + /* 0xd9 - CMP $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_1); + PRINT_OP (("AT PC: [%.2x - CMP $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_CMP_7: + /* 0xc1 - CMP ($aa,X) */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_2); + PRINT_OP (("AT PC: [%.2x - CMP ($%x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CMP_8: + /* 0xd1 - CMP ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + /* Compare value. */ + CompareReg (cpu, cpu->a, param8_2); + PRINT_OP (("AT PC: [%.2x - CMP ($%x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CPX_1: + /* 0xe0 - CPX #aa */ + + param8_1 = cpu->memRead (++cpu->pc); + CompareReg (cpu, cpu->x, param8_1); + PRINT_OP (("AT PC: [%.2x - CPX #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CPX_2: + /* 0xe4 - CPX $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + CompareReg (cpu, cpu->x, param8_2); + PRINT_OP (("AT PC: [%.2x - CPX $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CPX_3: + /* 0xec - CPX $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + CompareReg (cpu, cpu->x, param8_2); + PRINT_OP (("AT PC: [%.2x - CPX $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_CPY_1: + /* 0xc0 - CPY #aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + CompareReg (cpu, cpu->y, param8_1); + PRINT_OP (("AT PC: [%.2x - CPY #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CPY_2: + /* 0xc4 - CPY $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + CompareReg (cpu, cpu->y, param8_2); + PRINT_OP (("AT PC: [%.2x - CPY $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_CPY_3: + /* 0xcc - CPY $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + CompareReg (cpu, cpu->y, param8_2); + PRINT_OP (("AT PC: [%.2x - CPY $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ORA_1: + /* 0x09 - ORA #aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + value = cpu->a; + value |= param8_1; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ORA_2: + /* 0x05 - ORA $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ORA_3: + /* 0x15 - ORA $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + value = cpu->a; + value |= param8_2; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ORA_4: + /* 0x0d - ORA $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the operande. */ + param8_1 = cpu->memRead (param16); + + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ORA_5: + /* 0x1d - ORA $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the operande. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ORA_6: + /* 0x19 - ORA $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read the operande. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ORA_7: + /* 0x01 - ORA ($aa,X) */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ORA_8: + /* 0x11 - ORA ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + value = cpu->a; + value |= param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - ORA ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_AND_1: + /* 0x29 - AND #aa */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + value = cpu->a & param8_1; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_AND_2: + /* 0x25 - AND $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + /* Make the Addition. */ + value = cpu->a & param8_2; + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_AND_3: + /* 0x35 - AND $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Make the Addition. */ + value = cpu->a & param8_2; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_AND_4: + /* 0x2d - AND $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read the operande. */ + param8_1 = cpu->memRead (param16); + + value = cpu->a & param8_1; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_AND_5: + /* 0x3d - AND $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read the operande. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + value = cpu->a & param8_1; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_AND_6: + /* 0x39 - AND $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read the operande. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + value = cpu->a & param8_1; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_AND_7: + /*0x21 - AND ($aa,X) */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* Make the Addition. */ + value = cpu->a & param8_2; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_AND_8: + /* 0x31 - AND ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + /* Make the Addition. */ + value = cpu->a & param8_2; + + SetA (cpu, value); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - AND ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_BCS: + /* 0xb0 - BCS - Branch if Carry Set */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BCS $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfCarrySet (cpu, param8_1); + break; + case OP_CODE_BCC: + /* 0x90 - BCC - Branch if Carry Clear */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BCC $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfCarryClear (cpu, param8_1); + break; + case OP_CODE_BVC: + /* 0x50 - BVC - Branch if Overflow Clear */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BVC $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfOverflowClear (cpu, param8_1); + break; + case OP_CODE_BVS: + /* 0x70 - BVS - Branch if Overflow Set */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BVS $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfOverflowSet (cpu, param8_1); + break; + case OP_CODE_BNE: + /* 0xd0 - BNE - Branch if not Equal */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BNE $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfNotEqual (cpu, param8_1); + break; + case OP_CODE_BEQ: + /* 0xf0 - BEQ - Branch if Equal */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + cpu->pc++; + PRINT_OP (("AT PC: [%.2x - BEQ $%.4x]\n", opcode, + cpu->pc + (int8_t)param8_1)); + BranchIfEqual (cpu, param8_1); + break; + case OP_CODE_JSR: + /* 0x20 - JSR - Jump to SubRoutine */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Save the Current PC in the Stack. */ + param8_1 = (cpu->pc & 0xFF00) >> 8; + param8_2 = (cpu->pc & 0xFF); + + Push (cpu, param8_1); + Push (cpu, param8_2); + PRINT_OP (("AT PC: [%.2x - JSR $%.4x]\n", opcode, param16)); + + /* Jump to Sub Routine. */ + cpu->pc = param16; + break; + case OP_CODE_JMP_1: + /* 0x4c - JMP $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + PRINT_OP (("AT PC: [%.2x - JMP $%.4x]\n", opcode, param16)); + /* Jump to the adress. */ + cpu->pc = param16; + break; + case OP_CODE_JMP_2: + /* 0x6c - JMP ($aaaa) */ + + /* Le 6502 a un bug sur les sauts de pages indirect. + * Si on fait un faut sur une fin de page (02ff) + * La retenue sur le mot suivant n'est pas reporte. + * Donc plutot que de lire 02ff et 0300 on lit 02FF et 0200. + */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read the indexed pointer. */ + /* -Low part. */ + value = cpu->memRead (param16); + /* -Hight part. */ + param16_2 = (param16 & 0xFF00) | ((param16 + 1) &0xFF); + + value |= cpu->memRead (param16_2) << 8; + + PRINT_OP (("AT PC: [%.2x - JMP ($%.4x)]\n", opcode, param16)); + /* Jump to the adress. */ + cpu->pc = value; + break; + case OP_CODE_DEY: + /* 0x88 - DEY - Decrement Y */ + + DecY(cpu); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - DEY]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_DEX: + /* 0xca - DEX - Decrement X */ + + DecX(cpu); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - DEX]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_INY: + /* 0xc8 - INY - Increment Y */ + + IncY(cpu); + UpdateFlagsN_Z (cpu, cpu->y); + PRINT_OP (("AT PC: [%.2x - INY]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_INX: + /* 0xe8 - INX - Increment X */ + + IncX(cpu); + UpdateFlagsN_Z (cpu, cpu->x); + PRINT_OP (("AT PC: [%.2x - INX]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_INC_1: + /* 0xe6 - INC $aa */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Memory Value */ + param8_2 = cpu->memRead (param8_1); + + /* Increment the value. */ + param8_2++; + + /* Save the New Value. */ + cpu->memWrite (param8_1, param8_2); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_2); + PRINT_OP (("AT PC: [%.2x - INC $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_INC_2: + /* 0xf6 - INC $aa,X */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Memory Value */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Increment the value. */ + param8_2++; + + /* Save the New Value. */ + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, param8_2); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_2); + PRINT_OP (("AT PC: [%.2x - INC $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_INC_3: + /* 0xee - INC $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Memory Value */ + param8_1 = cpu->memRead (param16); + + /* Increment the value. */ + param8_1++; + + /* Save the New Value. */ + cpu->memWrite (param16, param8_1); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_1); + PRINT_OP (("AT PC: [%.2x - INC $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_INC_4: + /* 0xfe - INC $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Memory Value */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* Increment the value. */ + param8_1++; + + /* Save the New Value. */ + cpu->memWrite (param16 + cpu->x, param8_1); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_1); + PRINT_OP (("AT PC: [%.2x - INC $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_DEC_1: + /* 0xc6 - DEC $aa */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Memory Value */ + param8_2 = cpu->memRead (param8_1); + + /* Decrement the value. */ + param8_2--; + + /* Save the New Value. */ + cpu->memWrite (param8_1, param8_2); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_2); + PRINT_OP (("AT PC: [%.2x - DEC $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_DEC_2: + /* 0xd6 - DEC $aa,X */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Memory Value */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Decrement the value. */ + param8_2--; + + /* Save the New Value. */ + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, param8_2); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_2); + PRINT_OP (("AT PC: [%.2x - DEC $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_DEC_3: + /* 0xce - DEC $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Memory Value */ + param8_1 = cpu->memRead (param16); + + /* decrement the value. */ + param8_1--; + + /* Save the New Value. */ + cpu->memWrite (param16, param8_1); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_1); + PRINT_OP (("AT PC: [%.2x - DEC $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_DEC_4: + /* 0xde - DEC $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Memory Value */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* Decrement the value. */ + param8_1--; + + /* Save the New Value. */ + cpu->memWrite (param16 + cpu->x, param8_1); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, param8_1); + PRINT_OP (("AT PC: [%.2x - DEC $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ADC_1: + /* 0x69 - ADC #aa */ + + /* Read parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - ADC #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ADC_2: + /* 0x65 - ADC $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - ADC $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ADC_3: + /* 0x75 - ADC $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - ADC $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ADC_4: + /* 0x6d - ADC $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - ADC $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ADC_5: + /* 0x7d - ADC $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - ADC $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ADC_6: + /* 0x79 - ADC $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - ADC $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ADC_7: + /* 0x61 - ADC ($aa,X) */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - ADC ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ADC_8: + /* 0x71 - ADC ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + /* Make the Addition. */ + AddWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - ADC ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_SBC_1: + /* 0xe9 - SBC #aa */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - SBC #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_SBC_2: + /* 0xe5 - SBC $aa */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Operande. */ + param8_2 = cpu->memRead (param8_1); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - SBC $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_SBC_3: + /* 0xf5 - SBC $aa,X */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* Read Operande. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - SBC $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_SBC_4: + /* 0xed - SBC $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Operande. */ + param8_1 = cpu->memRead (param16); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - SBC $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_SBC_5: + /* SBC $aaaa,X */ + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Operande. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - SBC $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_SBC_6: + /* 0xfd - SBC $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Operande. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - SBC $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_SBC_7: + /* 0xe1 - SBC ($aa,X) */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Operande. */ + param8_2 = cpu->memRead (param16); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - SBC ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_SBC_8: + /* 0xf1 - SBC ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Operande. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + /* Make the subtract. */ + SubstractWithCarry (cpu, param8_2); + + PRINT_OP (("AT PC: [%.2x - SBC ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_BIT_1: + /* 0x24 - BIT $aa */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + + PRINT_OP (("AT PC: [%.2x - BIT $%.2x]\n", opcode, param8_1)); + + Bit_Test (cpu, param8_1); + cpu->pc++; + break; + case OP_CODE_BIT_2: + /* 0x2c - BIT $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + PRINT_OP (("AT PC: [%.2x - BIT $%.4x]\n", opcode, param16)); + + Bit_Test (cpu, param16); + cpu->pc++; + break; + case OP_CODE_ASL_1: + /* 0x0a - ASL A */ + + /* Make the shift Left. */ + UpdateFlagsC_L (cpu, cpu->a); + SetA (cpu, (cpu->a << 1) & 0xFF); + UpdateFlagsN_Z (cpu, cpu->a); + + PRINT_OP (("AT PC: [%.2x - ASL A]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_ASL_2: + /* 0x06 - ASL $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + /* If the bit 8 is 1, Then we Put Carry Status to 1. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Make the shift Left. */ + SetA (cpu, (param8_2 << 1) & 0xFF); + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param8_1, param8_2); + + PRINT_OP (("AT PC: [%.2x - ASL $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ASL_3: + /* 0x16 - ASL $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* If the bit 8 is 1, Then we Put Carry Status to 1. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Make the shift Left. */ + SetA (cpu, (param8_2 << 1) & 0xFF); + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, param8_2); + + PRINT_OP (("AT PC: [%.2x - ASL $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ASL_4: + /* 0x0e - ASL $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* If the bit 8 is 1, Then we Put Carry Status to 1. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Make the shift Left. */ + SetA (cpu, (param8_2 << 1) & 0xFF); + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param16, param8_2); + + PRINT_OP (("AT PC: [%.2x - ASL $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ASL_5: + /* 0x1e - ASL $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->x); + + /* If the bit 8 is 1, Then we Put Carry Status to 1. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Make the shift Left. */ + SetA (cpu, (param8_2 << 1) & 0xFF); + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param16 + cpu->x, param8_2); + + PRINT_OP (("AT PC: [%.2x - ASL $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LSR_1: + /* 0x4a - LSR A */ + + /* If the bit 0 is 1, Then we Put Carry Status to 0. */ + if (cpu->a & 0x1) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Make the shift Right. */ + SetA (cpu, (cpu->a >> 1) & 0xFF); + UpdateFlagsN_Z (cpu, cpu->a); + + PRINT_OP (("AT PC: [%.2x - LSR A]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_LSR_2: + /* 0x46 - LSR $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + /* If the bit 0 is 1, Then we Put Carry Status to 0. */ + if (param8_2 & 0x1) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Make the shift Right. */ + param8_2 = (param8_2 >> 1) & 0xFF; + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param8_1, param8_2); + + PRINT_OP (("AT PC: [%.2x - LSR $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LSR_3: + /* 0x56 - LSR $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* If the bit 0 is 1, Then we Put Carry Status to 0. */ + if (param8_2 & 0x1) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Make the shift Right. */ + param8_2 = (param8_2 >> 1) & 0xFF; + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, param8_2); + + PRINT_OP (("AT PC: [%.2x - LSR $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_LSR_4: + /* 0x4e - LSR $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* If the bit 0 is 1, Then we Put Carry Status to 0. */ + if (param8_2 & 0x1) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Make the shift Right. */ + param8_2 = (param8_2 >> 1) & 0xFF; + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param16, param8_2); + + PRINT_OP (("AT PC: [%.2x - LSR $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_LSR_5: + /* 0x5e - LSR $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->x); + + /* If the bit 0 is 1, Then we Put Carry Status to 0. */ + if (param8_2 & 0x1) { + bitset (&cpu->R_Status, STATUS_FLAG_C, 1); + } + else { + bitset (&cpu->R_Status, STATUS_FLAG_C, 0); + } + + /* Make the shift Right. */ + param8_2 = (param8_2 >> 1) & 0xFF; + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the right shift */ + cpu->memWrite (param16 + cpu->x, param8_2); + + PRINT_OP (("AT PC: [%.2x - LSR $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ROL_1: + /* 0x2a - ROL A */ + + param8_2 = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 1; + } + + /* Update the new CFlags. */ + UpdateFlagsC_L (cpu, cpu->a); + + /* Shift A. */ + value = (cpu->a << 1) & 0xFF; + value |= param8_2; + SetA (cpu, value); + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, cpu->a); + + PRINT_OP (("AT PC: [%.2x - ROL A]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_ROL_2: + /* 0x26 - ROL $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead (param8_1); + + tmp = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + tmp = 1; + } + + /* Update the new CFlags. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Shift A. */ + param8_2 = (param8_2 << 1) & 0xFF; + param8_2 |= tmp; + + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the rotation */ + cpu->memWrite (param8_1, param8_2); + + PRINT_OP (("AT PC: [%.2x - ROL $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ROL_3: + /* 0x36 - ROL $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + tmp = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + tmp = 1; + } + + /* Update the new CFlags. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Shift A. */ + param8_2 = (param8_2 << 1) & 0xFF; + param8_2 |= tmp; + + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the rotation */ + cpu->memWrite ((param8_1 + cpu->x) & 0xFF, param8_2); + + PRINT_OP (("AT PC: [%.2x - ROL $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ROL_4: + /* 0x2e - ROL $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + tmp = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + tmp = 1; + } + + /* Update the new CFlags. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Shift A. */ + param8_2 = (param8_2 << 1) & 0xFF; + param8_2 |= tmp; + + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the rotation */ + cpu->memWrite (param16, param8_2); + + PRINT_OP (("AT PC: [%.2x - ROL $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ROL_5: + /* 0x3e - ROL $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->x); + + tmp = 0; + + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + tmp = 1; + } + + /* Update the new CFlags. */ + UpdateFlagsC_L (cpu, param8_2); + + /* Shift A. */ + param8_2 = (param8_2 << 1) & 0xFF; + param8_2 += tmp; + + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, param8_2); + + /* Save the result of the rotation */ + cpu->memWrite (param16 + cpu->x, param8_2); + + PRINT_OP (("AT PC: [%.2x - ROL $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ROR_1: + /* 0x6a - ROR A */ + + param8_2 = 0; + + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 0x80; + } + + /* Update the new CFlags. */ + UpdateFlagsC_R (cpu, cpu->a); + + /* Shift A. */ + value = (cpu->a >> 1) & 0xFF; + value += param8_2; + SetA (cpu, value); + + /* Update Flag N & Z */ + UpdateFlagsN_Z (cpu, cpu->a); + + PRINT_OP (("AT PC: [%.2x - ROR A]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_ROR_2: + /* 0x66 - ROR $aa */ + + /* Read 8 bits Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_3 = cpu->memRead (param8_1); + + param8_2 = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 0x80; + } + + /* Update the new CFlags. */ + UpdateFlagsC_R (cpu, param8_3); + + /* Shift param8_1. */ + param8_3 = (param8_3 >> 1) & 0xFF; + param8_3 += (param8_2 << 7); + + UpdateFlagsN_Z (cpu, param8_3); + + cpu->memWrite (param8_1, param8_3); + + PRINT_OP (("AT PC: [%.2x - ROR $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ROR_3: + /* 0x76 - ROR $aa,X */ + + /* Read 8 bits Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Value. */ + param8_3 = cpu->memRead (param8_1 + cpu->x); + + param8_2 = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 0x80; + } + + /* Update the new CFlags. */ + UpdateFlagsC_R (cpu, param8_3); + + /* Shift param8_1. */ + param8_3 = (param8_3 >> 1) & 0xFF; + param8_3 += (param8_2 << 7); + + UpdateFlagsN_Z (cpu, param8_3); + + cpu->memWrite (param8_1 + cpu->x, param8_3); + + PRINT_OP (("AT PC: [%.2x - ROR $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_ROR_4: + /* 0x6e - ROR $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read Value. */ + param8_1 = cpu->memRead (param16); + + param8_2 = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 0x80; + } + + /* Update the new CFlags. */ + UpdateFlagsC_R (cpu, param8_1); + + /* Shift param8_1. */ + param8_1 = (param8_1 >> 1) & 0xFF; + param8_1 += (param8_2 << 7); + + UpdateFlagsN_Z (cpu, param8_1); + + cpu->memWrite (param16, param8_1); + + PRINT_OP (("AT PC: [%.2x - ROR $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_ROR_5: + /* 0x7e - ROR $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + param8_2 = 0; + /* Get Carry. */ + if (cpu->R_Status & FLAG_C) { + param8_2 = 0x80; + } + + /* Update the new CFlags. */ + UpdateFlagsC_R (cpu, param8_1); + + /* Shift param8_1. */ + param8_1 = (param8_1 >> 1) & 0xFF; + param8_1 += (param8_2 << 7); + + UpdateFlagsN_Z (cpu, param8_1); + + cpu->memWrite (param16 + cpu->x, param8_1); + + PRINT_OP (("AT PC: [%.2x - ROR $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_PHA: + /* 0x68 - PLA - Pull A (Pop) */ + + Push (cpu, cpu->a); + + PRINT_OP (("AT PC: [%.2x - PHA]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_PLA: + /* 0x68 - PLA - Pull A (Pop) */ + + SetA (cpu, Pop (cpu)); + + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - PLA]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_PHP: + /* 0x08 - PHP - Push Processor Status Register */ + + param8_1 = cpu->R_Status; + + bitset (¶m8_1, STATUS_FLAG_R, 1); + bitset (¶m8_1, STATUS_FLAG_B, 1); + + Push (cpu, param8_1); + + PRINT_OP (("AT PC: [%.2x - PHP]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_PLP: + /* 0x28 - PLP - Pull Processor Status Register */ + + param8_1 = Pop (cpu); + + /* Remove Flags. */ + bitset (¶m8_1, STATUS_FLAG_R, 0); + bitset (¶m8_1, STATUS_FLAG_B, 0); + + cpu->R_Status = param8_1; + PRINT_OP (("AT PC: [%.2x - PLP]\n", opcode)); + cpu->pc++; + break; + case OP_CODE_EOR_1: + /* 0x49 - EOR #aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_1; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR #$%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_EOR_2: + /* 0x45 - EOR $aa */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Memory Value */ + param8_2 = cpu->memRead (param8_1); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_2; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR $%.2x]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_EOR_3: + /* 0x55 - EOR $aa,X */ + + /* Read Parameter. */ + param8_1 = cpu->memRead (++cpu->pc); + /* Read Memory Value */ + param8_2 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_2; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR $%.2x,X]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_EOR_4: + /* 0x4d - EOR $aaaa */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_1; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR $%.4x]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_EOR_5: + /* 0x5d - EOR $aaaa,X */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->x); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_1; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR $%.4x,X]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_EOR_6: + /* 0x59 - EOR $aaaa,Y */ + + /* Read 16 bits Parameter */ + /* -Low part. */ + param16 = cpu->memRead (++cpu->pc); + /* -Hight part. */ + param16 |= cpu->memRead (++cpu->pc) << 8; + + /* Read Value. */ + param8_1 = cpu->memRead (param16 + cpu->y); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_1; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR $%.4x,Y]\n", opcode, param16)); + cpu->pc++; + break; + case OP_CODE_EOR_7: + /* 0x41 - EOR ($aa,X) */ + + /* Read Memory Value */ + param8_1 = cpu->memRead (++cpu->pc); + + /* -Low part. */ + param16 = cpu->memRead ((param8_1 + cpu->x) & 0xFF); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + cpu->x + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_2; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR ($%.2x,X)]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_EOR_8: + /* 0x51 - EOR ($aa),Y */ + + /* Read Parameter */ + param8_1 = cpu->memRead (++cpu->pc); + /* -Low part. */ + param16 = cpu->memRead (param8_1); + /* -Hight part. */ + param16 |= cpu->memRead ((param8_1 + 1) & 0xFF) << 8; + + /* Read Value. */ + param8_2 = cpu->memRead (param16 + cpu->y); + + /* a XOR b */ + /* a xor b = (a et ! b) ou (! a et b) */ + value = cpu->a ^ param8_2; + SetA (cpu, value); + + /* And Update N and Z Flags. */ + UpdateFlagsN_Z (cpu, cpu->a); + PRINT_OP (("AT PC: [%.2x - EOR ($%.2x),Y]\n", opcode, param8_1)); + cpu->pc++; + break; + case OP_CODE_RTS: + /* 0x60 - RTS - Return from SubRoutine */ + + /* Get the PC saved on the stack. */ + /* -Low part. */ + param8_2 = Pop (cpu); + /* -Hight part. */ + param8_1 = Pop (cpu); + + /* Save param in a 16 bit parameter. */ + param16 = param8_2; + param16 |= param8_1 << 8; + PRINT_OP (("AT PC: [%x - RTS]\n", opcode)); + /* Return to last instruction (before the jump). */ + cpu->pc = param16; + /* And go to the next instruction. */ + cpu->pc++; + break; + case OP_CODE_RTI: + /* 0x40 - RTI - Return from Interrupt */ + + /* Get the Status */ + cpu->R_Status = Pop (cpu); + + /* Get the PC saved on the stack. */ + /* -Low part. */ + param8_2 = Pop (cpu); + /* -Hight part. */ + param8_1 = Pop (cpu); + + /* Save param in a 16 bit parameter. */ + param16 = param8_2; + param16 |= param8_1 << 8; + + PRINT_OP (("AT PC: [%.2x - RTI]\n", opcode)); + /* Now we accept New NMI. */ + cpu->pc = param16; + break; + case OP_CODE_NOP: + /* 0xea - NOP - No Operation */ + + PRINT_OP (("AT PC: [%x - NOP]\n", opcode)); + /* Go to the next instruction. */ + cpu->pc++; + break; + default: + DEBUG0 (("Unknown OPCODE: (0x%x)\n", opcode)); + result = -1; + } + + return result; +} diff --git a/src/cpu/cpu6502.h b/src/cpu/cpu6502.h new file mode 100644 index 0000000..adf7746 --- /dev/null +++ b/src/cpu/cpu6502.h @@ -0,0 +1,94 @@ +/*---------------------------------------------------------------------------- + * cpu6502.h: + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __CPU6502_H +#define __CPU6502_H + +/* + * Status: + * ====== + * +-----+-----+-----+-----+-----+-----+-----+-----+ + * | | | | | | | | | + * | N | V | R | B | D | I | Z | C | + * | | | | | | | | | + * +-----+-----+-----+-----+-----+-----+-----+-----+ + * + * C: Carry Flag (Bit de retenu) + * Z: Zero Flag (Bit d'etat Zero) + * I: Interrupt Disable Flag + * D: Decimal Mode (Mode décimal) + * B: Break Command (Bit de Break) + * R: Reserved + * V: Overflow Flag (Bit de depassement signé) + * N: Negative Flag (Bit de negation) +*/ + +#define STATUS_FLAG_C 0 +#define STATUS_FLAG_Z 1 +#define STATUS_FLAG_I 2 +#define STATUS_FLAG_D 3 +#define STATUS_FLAG_B 4 +#define STATUS_FLAG_R 5 +#define STATUS_FLAG_V 6 +#define STATUS_FLAG_N 7 + + +#define FLAG_C 0x1 + +#define STACK_START 0xFF +#define STACK_END 0x100 + +/* Overflow flag */ +#define V_FLAG 0xFF00 +#define B_FLAG (1 << STATUS_FLAG_B) +// AVANT #define V_FLAG (1 << 6) + + +/* Structure for the Debug's Alert support of registers. */ +typedef struct nes_DebugCpuAlert_t { + + /* Boolean to know if an alert is set or not. */ + uint8_t active; + + int16_t a; + int16_t x; + int16_t y; + +}nes_DebugCpuAlert_t; + + +/* Main structure of the NES's CPU. */ +typedef struct nes_cpu6502_t { + uint8_t a; + uint8_t x; + uint8_t y; + uint8_t R_Stack; + uint8_t R_Status; + uint16_t pc; + + /* Fonction to access to the Central Memory. */ + uint8_t (*memRead) (uint16_t addr); + void (*memWrite) (uint16_t addr, uint8_t value); + + /* Counter of Cycle to know where we are. */ + int16_t nbCycles; + + /* Alert on the registers. */ + nes_DebugCpuAlert_t alert; + +}nes_cpu6502_t; + + +/* Exported functions. */ +extern int cpuReset (nes_cpu6502_t *cpu); +extern int cpu6502_execOpCode (nes_cpu6502_t *cpu, uint8_t opcode); + +#endif diff --git a/src/cpu/cyclesTable.h b/src/cpu/cyclesTable.h new file mode 100644 index 0000000..49b4f61 --- /dev/null +++ b/src/cpu/cyclesTable.h @@ -0,0 +1,40 @@ +/*---------------------------------------------------------------------------- + * cycleTable.h: This file contain the array of the number of cycles, each + * opcode take. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __CYCLETABLE_H +#define __CYCLETABLE_H + + + +/* Number of cycles for the 256 opcodes of the 6502 CPU. */ + +uint8_t OpcodesCycles[256] = +{ + 7, 6, 2, 1, 5, 3, 5, 5, 3, 2, 2, 1, 6, 4, 6, 2, + 2, 5, 5, 1, 5, 4, 6, 5, 2, 4, 2, 1, 6, 4, 6, 2, + 6, 6, 2, 1, 3, 3, 5, 5, 4, 2, 2, 1, 4, 4, 6, 2, + 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 2, 1, 4, 4, 6, 2, + 6, 6, 2, 1, 3, 3, 5, 5, 3, 2, 2, 1, 3, 4, 6, 2, + 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 3, 1, 8, 4, 6, 2, + 6, 6, 2, 1, 3, 3, 5, 5, 4, 2, 2, 1, 6, 4, 6, 2, + 2, 5, 5, 1, 4, 4, 6, 5, 5, 4, 4, 1, 6, 4, 6, 2, + 3, 6, 2, 1, 3, 3, 3, 5, 2, 2, 2, 1, 4, 4, 4, 2, + 2, 6, 5, 1, 4, 4, 4, 5, 2, 5, 2, 1, 4, 5, 5, 2, + 2, 6, 2, 1, 3, 3, 3, 5, 2, 2, 2, 1, 4, 4, 4, 2, + 2, 5, 5, 1, 4, 4, 4, 5, 2, 4, 2, 1, 4, 4, 4, 2, + 2, 6, 2, 1, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 2, + 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 3, 2, 4, 4, 6, 2, + 2, 6, 2, 1, 3, 3, 5, 5, 2, 2, 2, 1, 4, 4, 6, 2, + 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 4, 1, 4, 4, 6, 2 +}; + +#endif diff --git a/src/cpu/opcodes.h b/src/cpu/opcodes.h new file mode 100644 index 0000000..a7ce6c9 --- /dev/null +++ b/src/cpu/opcodes.h @@ -0,0 +1,190 @@ +/*---------------------------------------------------------------------------- + * 6502: opcodes.h. This file contain the list of the opcodes of the cpu. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + + +#ifndef _6502_OPCODES_H +#define _6502_OPCODES_H + +#define OP_CODE_BRK 0x00 /* Break. Soft Interrupt. */ + +#define OP_CODE_SEI 0x78 /* SEI - Set Interrupt disable. */ +#define OP_CODE_SED 0xf8 /* SED - Set Decimal Mode. */ +#define OP_CODE_SEC 0x38 /* SEC - Set Carry Flag. */ +#define OP_CODE_CLC 0x18 /* CLC - Clear Carry. */ +#define OP_CODE_CLD 0xd8 /* Clear Decimal Mode. */ +#define OP_CODE_CLV 0xb8 /* Clear Overflow Flag. */ + /* LoaD Accumulator Charge dans le registre A. */ +#define OP_CODE_LDA_1 0xa9 /* LDA #aa */ +#define OP_CODE_LDA_2 0xa5 /* LDA $aa */ +#define OP_CODE_LDA_3 0xb5 /* LDA $aa,X */ +#define OP_CODE_LDA_4 0xad /* LDA $aaaa */ +#define OP_CODE_LDA_5 0xbd /* LDA $aaaa, X */ +#define OP_CODE_LDA_6 0xb9 /* LDA $aaaa, Y */ +#define OP_CODE_LDA_7 0xa1 /* LDA ($aa,X) */ +#define OP_CODE_LDA_8 0xb1 /* LDA ($aa),Y */ + /* Load Register X */ +#define OP_CODE_LDX_1 0xa2 /* LDX #aa */ +#define OP_CODE_LDX_2 0xa6 /* LDX $aa */ +#define OP_CODE_LDX_3 0xb6 /* LDX $aa,Y */ +#define OP_CODE_LDX_4 0xae /* LDX $aaaa */ +#define OP_CODE_LDX_5 0xbe /* LDX $aaaa,Y */ + /* Load Register Y */ +#define OP_CODE_LDY_1 0xa0 /* LDY #aa */ +#define OP_CODE_LDY_2 0xa4 /* LDY $aa */ +#define OP_CODE_LDY_3 0xb4 /* LDY $aa,X */ +#define OP_CODE_LDY_4 0xac /* LDY $aaaa */ +#define OP_CODE_LDY_5 0xbc /* LDY $aaaa,X */ + /* STore Accumulator */ +#define OP_CODE_STA_1 0x85 /* STA $aa */ +#define OP_CODE_STA_2 0x95 /* STA $aa,X */ +#define OP_CODE_STA_3 0x8d /* STA $aaaa */ +#define OP_CODE_STA_4 0x9d /* STA $aaaa,X */ +#define OP_CODE_STA_5 0x99 /* STA $aaaa,Y */ +#define OP_CODE_STA_6 0x81 /* STA ($aa,X) */ +#define OP_CODE_STA_7 0x91 /* STA ($aa),Y */ + /* STX - Store X Register */ +#define OP_CODE_STX_1 0x86 /* STX $aa */ +#define OP_CODE_STX_2 0x96 /* STX $aa,Y */ +#define OP_CODE_STX_3 0x8e /* STX $aaaa */ + /* STY - Store Y Register */ +#define OP_CODE_STY_1 0x84 /* STY $aa */ +#define OP_CODE_STY_2 0x94 /* STY $aa,X */ +#define OP_CODE_STY_3 0x8c /* STY $aaaa */ +#define OP_CODE_TXS 0x9a /* Transfert X to Stack. */ +#define OP_CODE_TXA 0x8a /* TXA - Transfer X to Register A */ +#define OP_CODE_TYA 0x98 /* TYA - Transfer Y to Register A */ +#define OP_CODE_TAX 0xaa /* TAX - Transfer Accumulator to X */ +#define OP_CODE_TAY 0xa8 /* TAY - Transfer Accumulator to Y */ +#define OP_CODE_TSX 0xba /* TSX - Transfer Stack To X */ +#define OP_CODE_BPL 0x10 /* BPL - Branch on Plus */ +#define OP_CODE_BMI 0x30 /* BMI - Branch if Minus */ + /* Compare Memory And Accumulator */ +#define OP_CODE_CMP_1 0xc9 /* CMP #aa */ +#define OP_CODE_CMP_2 0xc5 /* CMP $aa */ +#define OP_CODE_CMP_3 0xd5 /* CMP $aa,X */ +#define OP_CODE_CMP_4 0xcd /* CMP $aaaa */ +#define OP_CODE_CMP_5 0xdd /* CMP $aaaa,X */ +#define OP_CODE_CMP_6 0xd9 /* CMP $aaaa,Y */ +#define OP_CODE_CMP_7 0xc1 /* CMP ($aa,X) */ +#define OP_CODE_CMP_8 0xd1 /* CMP ($aa),Y */ + /* CPX - Compare Memory And X */ +#define OP_CODE_CPX_1 0xe0 /* CPX #aa */ +#define OP_CODE_CPX_2 0xe4 /* CPX $aa */ +#define OP_CODE_CPX_3 0xec /* CPX $aaaa */ + /* CPY - Compare Memory And Y */ +#define OP_CODE_CPY_1 0xc0 /* CPY #aa */ +#define OP_CODE_CPY_2 0xc4 /* CPY $aa */ +#define OP_CODE_CPY_3 0xcc /* CPY $aaaa */ + /* ORA - Logical Inclusive OR */ +#define OP_CODE_ORA_1 0x09 /* ORA #aa */ +#define OP_CODE_ORA_2 0x05 /* ORA $aa */ +#define OP_CODE_ORA_3 0x15 /* ORA $aa,X */ +#define OP_CODE_ORA_4 0x0d /* ORA $aaaa */ +#define OP_CODE_ORA_5 0x1d /* ORA $aaaa,X */ +#define OP_CODE_ORA_6 0x19 /* ORA $aaaa,Y */ +#define OP_CODE_ORA_7 0x01 /* ORA ($aa,X) */ +#define OP_CODE_ORA_8 0x11 /* ORA ($aa),Y */ +#define OP_CODE_BCS 0xb0 /* BCS - Branch if Carry Set */ +#define OP_CODE_BCC 0x90 /* BCC - Branch if Carry Clear */ +#define OP_CODE_BVC 0x50 /* BVC - Branch if Overflow Clear */ +#define OP_CODE_BVS 0x70 /* BVS - Branch if Overflow Set */ +#define OP_CODE_JSR 0x20 /* JSR - Jump to SubRoutine */ + /* Jump. */ +#define OP_CODE_JMP_1 0x4c /* JMP $aaaa */ +#define OP_CODE_JMP_2 0x6c /* JMP ($aaaa) */ +#define OP_CODE_BNE 0xd0 /* BNE - Branch if not Equal */ +#define OP_CODE_BEQ 0xf0 /* BEQ - Branch if Equal */ +#define OP_CODE_DEY 0x88 /* DEY - Decrement Y */ +#define OP_CODE_DEX 0xca /* DEX - Decrement X */ +#define OP_CODE_INY 0xc8 /* INY - Increment Y */ +#define OP_CODE_INX 0xe8 /* INX - Increment X */ + /* INC - Increment Memory */ +#define OP_CODE_INC_1 0xe6 /* INC $aa */ +#define OP_CODE_INC_2 0xf6 /* INC $aa,X */ +#define OP_CODE_INC_3 0xee /* INC $aaaa */ +#define OP_CODE_INC_4 0xfe /* INC $aaaa,X */ + /* DEC - Decrement Source */ +#define OP_CODE_DEC_1 0xc6 /* DEC $aa */ +#define OP_CODE_DEC_2 0xd6 /* DEC $aa,X */ +#define OP_CODE_DEC_3 0xce /* DEC $aaaa */ +#define OP_CODE_DEC_4 0xde /* DEC $aaaa,X */ + /* ADC - Add with Carry */ +#define OP_CODE_ADC_1 0x69 /* ADC #aa */ +#define OP_CODE_ADC_2 0x65 /* ADC $aa */ +#define OP_CODE_ADC_3 0x75 /* ADC $aa,X */ +#define OP_CODE_ADC_4 0x6d /* ADC $aaaa */ +#define OP_CODE_ADC_5 0x7d /* ADC $aaaa,X */ +#define OP_CODE_ADC_6 0x79 /* ADC $aaaa,Y */ +#define OP_CODE_ADC_7 0x61 /* ADC ($aa,X) */ +#define OP_CODE_ADC_8 0x71 /* ADC ($aa),Y */ + /* SBC - Substract with Carry */ +#define OP_CODE_SBC_1 0xe9 /* SBC #aa */ +#define OP_CODE_SBC_2 0xe5 /* SBC $aa */ +#define OP_CODE_SBC_3 0xf5 /* SBC $aa,X */ +#define OP_CODE_SBC_4 0xed /* SBC $aaaa */ +#define OP_CODE_SBC_5 0xfd /* SBC $aaaa,X */ +#define OP_CODE_SBC_6 0xf9 /* SBC $aaaa,Y */ +#define OP_CODE_SBC_7 0xe1 /* SBC ($aa,X) */ +#define OP_CODE_SBC_8 0xf1 /* SBC ($aa),Y */ + /* BIT - Bit Test */ +#define OP_CODE_BIT_1 0x24 /* BIT $aa */ +#define OP_CODE_BIT_2 0x2c /* BIT $aaaa */ + /* AND - Logical AND */ +#define OP_CODE_AND_1 0x29 /* AND #aa */ +#define OP_CODE_AND_2 0x25 /* AND $aa */ +#define OP_CODE_AND_3 0x35 /* AND $aa,X */ +#define OP_CODE_AND_4 0x2d /* AND $aaaa */ +#define OP_CODE_AND_5 0x3d /* AND $aaaa,X */ +#define OP_CODE_AND_6 0x39 /* AND $aaaa,Y */ +#define OP_CODE_AND_7 0x21 /* AND ($aa,X) */ +#define OP_CODE_AND_8 0x31 /* AND ($aa),Y */ + /* LSR - Logical Shift Right */ +#define OP_CODE_LSR_1 0x4a /* LSR A */ +#define OP_CODE_LSR_2 0x46 /* LSR $aa */ +#define OP_CODE_LSR_3 0x56 /* LSR $aa,X */ +#define OP_CODE_LSR_4 0x4e /* LSR $aaaa */ +#define OP_CODE_LSR_5 0x5e /* LSR $aaaa,X */ + /* ROL - Rotate Left */ +#define OP_CODE_ROL_1 0x2a /* ROL A */ +#define OP_CODE_ROL_2 0x26 /* ROL $aa */ +#define OP_CODE_ROL_3 0x36 /* ROL $aa,X */ +#define OP_CODE_ROL_4 0x2e /* ROL $aaaa */ +#define OP_CODE_ROL_5 0x3e /* ROL $aaaa,X */ + /* ROR - Rotate Right */ +#define OP_CODE_ROR_1 0x6a /* ROR A */ +#define OP_CODE_ROR_2 0x66 /* ROR $aa */ +#define OP_CODE_ROR_3 0x76 /* ROR $aa,X */ +#define OP_CODE_ROR_4 0x6e /* ROR $aaaa */ +#define OP_CODE_ROR_5 0x7e /* ROR $aaaa,X */ + /* ASL - Arithmetic Shift Left */ +#define OP_CODE_ASL_1 0x0a /* ASL A */ +#define OP_CODE_ASL_2 0x06 /* ASL $aa */ +#define OP_CODE_ASL_3 0x16 /* ASL $aa,X */ +#define OP_CODE_ASL_4 0x0e /* ASL $aaaa */ +#define OP_CODE_ASL_5 0x1e /* ASL $aaaa,X */ +#define OP_CODE_PHA 0x48 /* PHA - Push A */ +#define OP_CODE_PLA 0x68 /* PLA - Pull A (Pop) */ +#define OP_CODE_PHP 0x08 /* PHP - Push Processor Status Register */ +#define OP_CODE_PLP 0x28 /* PLP - Pull Processor Status Register */ + /* EOR - Exclusive-OR */ +#define OP_CODE_EOR_1 0x49 /* EOR #aa */ +#define OP_CODE_EOR_2 0x45 /* EOR $aa */ +#define OP_CODE_EOR_3 0x55 /* EOR $aa,X */ +#define OP_CODE_EOR_4 0x4d /* EOR $aaaa */ +#define OP_CODE_EOR_5 0x5d /* EOR $aaaa,X */ +#define OP_CODE_EOR_6 0x59 /* EOR $aaaa,Y */ +#define OP_CODE_EOR_7 0x41 /* EOR ($aa,X) */ +#define OP_CODE_EOR_8 0x51 /* EOR ($aa),Y */ +#define OP_CODE_RTS 0x60 /* RTS - Return from SubRoutine */ +#define OP_CODE_RTI 0x40 /* RTI - Return from Interrupt */ +#define OP_CODE_NOP 0xea /* NOP - No Operation */ + +#endif diff --git a/src/debug.c b/src/debug.c new file mode 100644 index 0000000..3aecd51 --- /dev/null +++ b/src/debug.c @@ -0,0 +1,26 @@ +/*---------------------------------------------------------------------------- + * debug.c: + * Debug Function + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include +#include + +#include "debug.h" + +/******************************************************* + * This function print the Trace. +*/ +void DebugPrint (const char *format,...) +{ + va_list ap; + va_start(ap, format); + vprintf (format, ap); + va_end(ap); +} diff --git a/src/debug.h b/src/debug.h new file mode 100644 index 0000000..f046a5f --- /dev/null +++ b/src/debug.h @@ -0,0 +1,30 @@ +/*---------------------------------------------------------------------------- + * debug.h: + * Debug Function + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __DEBUG_H +#define __DEBUG_H + +extern void DebugPrint (const char *format,...); + +#ifdef DEBUG +# define DEBUG_REGS(a) printRegs(a) +# define DEBUG0(a) do { DebugPrint a; }while(0) +# define DEBUG1(a) +# define DEBUG2(a) +#else +# define DEBUG_REGS +# define DEBUG0(a) +# define DEBUG1(a) +# define DEBUG2(a) +#endif + + +#endif diff --git a/src/emulator/apu.c b/src/emulator/apu.c new file mode 100644 index 0000000..899ca4d --- /dev/null +++ b/src/emulator/apu.c @@ -0,0 +1,37 @@ +/*---------------------------------------------------------------------------- + * apu.c: Audio Processor Unit + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" + +#include "main.h" + +#include "debug.h" + + +/******************************************************* + * Init the APU Module. +*/ +int apu_init () +{ + int result = 0; + + return result; +} diff --git a/src/emulator/apu.h b/src/emulator/apu.h new file mode 100644 index 0000000..d568a80 --- /dev/null +++ b/src/emulator/apu.h @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * apu.h: Audio Processor Unit + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef _APU_H +#define _APU_H + + +#define APU_REGISTER_SIZE 0x18 + +typedef struct nes_apu_t { + /* Register of the APU. */ + unsigned char registers [APU_REGISTER_SIZE]; + +}nes_apu_t; + + +#endif + + diff --git a/src/emulator/debugger.c b/src/emulator/debugger.c new file mode 100644 index 0000000..d5f317c --- /dev/null +++ b/src/emulator/debugger.c @@ -0,0 +1,231 @@ +/*---------------------------------------------------------------------------- + * debugger.c: This files contain the main functions to have the debugger + * functionality under the nes emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 22/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "main.h" + +#include "debug.h" + + +/******************************************************* + * Put an Alert on the Register 'reg' when the value + * 'param' is set on it. + */ +void PutAlertRegister (uint8_t reg, uint16_t param) +{ + fprintf (stdout, "Put an Alert on the register %c, when the value " + "will be: %x\n", reg, param); + + switch (reg) { + case 'a': + emul.cpu.alert.a = param; + break; + case 'x': + emul.cpu.alert.x = param; + break; + case 'y': + emul.cpu.alert.y = param; + break; + default: + fprintf (stdout, "Unknown Register: %c(%d)\n", reg, reg); + } + + /* Active the alert. */ + emul.cpu.alert.active = 1; + +} + +/******************************************************* + * Remove an alert on the register 'reg' + */ +void RemoveAlert (uint8_t reg) +{ + fprintf (stdout, "Remove the Alert for Register %c.\n", reg); + + /* Init the Alert Register. */ + switch (reg) { + case 'a': + emul.cpu.alert.a = -1; + break; + case 'x': + emul.cpu.alert.x = -1; + break; + case 'y': + emul.cpu.alert.y = -1; + break; + default: + fprintf (stdout, "Unknown Register: %c\n", reg); + } + + /* Remove the alert use if no more alert is active. */ + if ((emul.cpu.alert.a != -1) && (emul.cpu.alert.x != -1) && + (emul.cpu.alert.y != -1)) { + emul.cpu.alert.active = 0; + } +} + +/******************************************************* + * This function is the main function of the debugger. + */ +int debuggerMain (void *unused) +{ + char buffer [50]; + uint16_t param; + uint8_t reg; + + /* Get the Start Address of the Rom. */ + param = memory_Read16 (0xFFFD, 0xFFFC); + fprintf (stdout, "Rom start at: $%.4x\n", param); + /* Get the Start Address of the NMI. */ + param = memory_Read16 (0xFFFB, 0xFFFA); + fprintf (stdout, "NMI start at: $%.4x\n", param); + + while (emul.quit != 0) { + + fflush (stdin); + fprintf (stdout, "> "); + fgets (buffer, 50, stdin); + /* Manage the Actions */ + switch (buffer [0]) { + case 'h': + fprintf (stdout, "Help:\n"); + fprintf (stdout, "=====\n"); + fprintf (stdout, " - h: Display Help.\n"); + fprintf (stdout, " - Enter key: Launch the next instruction.\n"); + fprintf (stdout, " - q: Quit the Emulator.\n"); + fprintf (stdout, " - t xxxx: Set Pc to the address xxx.\n"); + fprintf (stdout, " - = xxxx: Put a break Point at the address xxxx.\n"); + fprintf (stdout, " - m xxxx: Display the memory at the address xxxx.\n"); + fprintf (stdout, " - a var=xx: Make an alert on the register var to" + " the value xx.\n"); + fprintf (stdout, " - s x : Show Tiles (x).\n"); + fprintf (stdout, " - s c: Clear Screen.\n"); + break; + case 0: + case 10: + SDL_mutexP (emul.debugger.mutexDebugger); + emul.debugger.debugExec = ONLY_ONE_OP; + SDL_mutexV (emul.debugger.mutexDebugger); + break; + case 'q': + fprintf (stdout, "Quit\n"); + emul.quit = 0; + break; + case 's': + + if (*(buffer+2) == 'c') { + fprintf (stdout, "Clear the PPU Screen.\n"); + PPU_ClearScreen (); + } + else { + sscanf (buffer+1, "%hd", ¶m); + PPU_ShowTiles (param); + } + break; + case 'c': + PPU_ClearScreen (); + break; + case 'm': + param = 0; + sscanf (buffer+1, "%hx", ¶m); + DumpMemory (param); + break; + case 'a': + if (strlen (buffer+1) == 4) { + reg = buffer[3]; + RemoveAlert (reg); + } + else if (strlen (buffer+1) < 5) { + fprintf (stdout, "Unknown syntax for the set alert.%d\n"); + fprintf (stdout, " exemples:\n"); + fprintf (stdout, " - a x=ff Add an alert on the register x.\n"); + fprintf (stdout, " - a rx remove the alert on the register x.\n"); + } + else { + reg = buffer[2]; + param = 0; + sscanf (buffer+4, "%hx", ¶m); + PutAlertRegister (reg, param); + SDL_mutexP (emul.debugger.mutexDebugger); + emul.debugger.debugExec = MANY_OPS; + SDL_mutexV (emul.debugger.mutexDebugger); + + } + break; + case 't': + param = 0; + /* Read the Address. */ + sscanf (buffer+1, "%hx", ¶m); + fprintf (stdout, "Set PC to: %x\n", param); + emul.cpu.pc = param; + break; + case '=': + param = 0; + /* Read the Address. */ + sscanf (buffer+1, "%hx", ¶m); + fprintf (stdout, "Set Break Point at: %x\n", param); + + SDL_mutexP (emul.debugger.mutexDebugger); + emul.debugger.debugExec = MANY_OPS; + emul.debugger.breakPoint = param; + SDL_mutexV (emul.debugger.mutexDebugger); + + break; + default: + fprintf (stdout, "Unknown commmand (%d).\n", buffer[0]); + } + } + + return 0; +} + +/******************************************************* + * This init the debugger. + */ +int debugger_init () +{ + int result = 0; + SDL_Thread *thread; + + DEBUG0 (("INIT Debug\n")); + + /* Create the Mutex for the Debugger. */ + emul.debugger.mutexDebugger = SDL_CreateMutex (); + + thread = SDL_CreateThread (debuggerMain, NULL); + if (thread == NULL) { + result = -1; + fprintf(stderr, "Unable to create thread: %s\n", SDL_GetError()); + } + + return result; +} + +/******************************************************* + * This stop the execution the debugger. + */ +void debugger_stop () +{ + SDL_mutexP (emul.debugger.mutexDebugger); + emul.debugger.debugExec = 0; + SDL_mutexV (emul.debugger.mutexDebugger); +} diff --git a/src/emulator/debugger.h b/src/emulator/debugger.h new file mode 100644 index 0000000..5f8be39 --- /dev/null +++ b/src/emulator/debugger.h @@ -0,0 +1,29 @@ +/*---------------------------------------------------------------------------- + * debugger.h: This files contain the main functions to have the debugger + * functionality under the nes emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 22/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __DEBUGGER_H +#define __DEBUGGER_H + +#define ONLY_ONE_OP 1 +#define MANY_OPS 2 + +# define PRINT_OP(a) if (emul.debugger.use == 1) {DebugPrint a;} else { DEBUG1 (a);} + +typedef struct debugger_t { + /* Mutex used to block/unblock the debugger. */ + SDL_mutex* mutexDebugger; + uint8_t debugExec; + uint8_t use; + uint16_t breakPoint; +} debugger_t; + +#endif diff --git a/src/emulator/emulator.c b/src/emulator/emulator.c new file mode 100644 index 0000000..dc99e48 --- /dev/null +++ b/src/emulator/emulator.c @@ -0,0 +1,464 @@ +/*---------------------------------------------------------------------------- + * emulator.c. Main function of the Emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "cyclesTable.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "main.h" +#include "nespal.h" + +#include "debug.h" + + +/* Local functions. */ +int Window_Init (); +int HandleEvent (SDL_Event *event); + +/* Global Emulator. */ +nes_emulator_t emul; + +/******************************************************* + * Init the Emulator. +*/ +int emulator_init () +{ + int result = 0; + + /* Init the variables. */ + emul.quit = 1; + emul.cpu.nbCycles = NB_CYCLES_MAX; + emul.nbLines = 0; + + /* Memory Init. */ + result = memory_init (); + if (result != 0) { + fprintf (stderr, "Impossible to Init Memory.\n"); + return -1; + } + + /* CPU Init. */ + + /* Set the Memory acces to the CPU. */ + emul.cpu.memRead = memory_Read; + emul.cpu.memWrite = memory_Write; + + result = cpu6502_init (); + if (result != 0) { + fprintf (stderr, "Impossible to Init CPU.\n"); + return -1; + } + + /* PPU Init. */ + result = ppu_init (); + if (result != 0) { + fprintf (stderr, "Impossible to Init PPU.\n"); + return -1; + } + + /* APU Init. */ + result = apu_init (); + if (result != 0) { + fprintf (stderr, "Impossible to Init APU.\n"); + return -1; + } + + /* Init the Paddles. */ + paddle_Init (&emul.Pad1); + paddle_Init (&emul.Pad2); + + /* SDL Init. */ + result = Window_Init (); + if (result != 0) { + fprintf (stderr, "Impossible to Init Window.\n"); + return -1; + } + + return result; +} + +/******************************************************* + * Load the Rom in the Emulator. +*/ +int emulator_load (char *romName) +{ + int result = 0; + int romfd; + int size, readSize; + int size_prgRom, size_chrRom; + unsigned char *romBuffer; + uint8_t mapper, mirroring, tmp; + fprintf (stdout, "Load <%s>\n", romName); + + /* Open ROM file */ + romfd = open (romName, O_RDONLY); + if (romfd < 0) { + fprintf(stderr,"Unable to open %s\n", romName); + } + /* Get the Size of the file. */ + size = lseek (romfd, 0, SEEK_END); + if (size < 0) { + fprintf (stderr, "Unable to read %s\n",romName); + return -1; + } + + /* Return to the beginning of the File. */ + lseek (romfd, 0, SEEK_SET); + + /* Allocate temporary buffer for the Rom File. */ + romBuffer = malloc (sizeof(char) * size); + if (romBuffer == NULL) { + fprintf (stderr, "Impossible to allocate rom buffer.\n"); + return -1; + } + + /* Read the Rom file. */ + readSize = read (romfd, romBuffer, size); + if (readSize <= 0) { + fprintf (stderr, "Impossible to read the rom file.\n"); + return readSize; + } + + /* Check if the open file is a NES Rom file. */ + if ((romBuffer[0] != 'N') && (romBuffer[1] != 'E') && + (romBuffer[2] != 'S')) { + fprintf (stderr, "The Rom File is not a NES rom. [%d,%d,%d]\n", + romBuffer[0], romBuffer[1], romBuffer[2]); + result = -1; + } + + /* Get Section Size */ + size_prgRom = romBuffer[4]; + size_chrRom = romBuffer[5]; + + fprintf (stderr, "prgRom: %d, chrRom: %d\n", size_prgRom, size_chrRom); + + /* Get the Mapper Number. */ + /* Get Lower part of the Mapper Number */ + tmp = romBuffer[6] >> 4; + mapper = tmp; + tmp = romBuffer[7] >> 4; + mapper |= (tmp << 4); + + /* TODO: We only support mapper0 */ + if (mapper != 0) { + fprintf (stderr, "Unsupported Mapper %d.\n", mapper); + return -1; + } + + fprintf (stdout, "Mapper: %d\n", mapper); + /* Get the Mirroring State. */ + mirroring = romBuffer[6] & 0x1; + + if (mirroring == 1) { + fprintf (stdout, "Mirroring Vertical.\n"); + } + else { + fprintf (stdout, "Mirroring Horizontal.\n"); + } + + /* Allocate the Rom Memory. */ + emul.memory.prgRom = malloc (MEMORY_PROGROM_SIZE); + if (emul.memory.prgRom == NULL) { + fprintf (stderr, "Impossible to allocate memory for Prg Rom.\n"); + return -1; + } + + /* Copy the program Rom. */ + if (size_prgRom == 1) { + memcpy (emul.memory.prgRom + (MEMORY_PROGROM_SIZE / 2), + romBuffer + 16, (1024 * 16 * size_prgRom)); + } + else { + memcpy (emul.memory.prgRom, romBuffer + 16, (1024 * 16 * size_prgRom)); + } + /* Copy the Data Rom. */ + memcpy (emul.ppu.vram, romBuffer + 16 + (1024 * 16 * size_prgRom), + (1024 * 8) * size_chrRom); + + /* Close the Rom file. */ + close (romfd); + + /* Finally Clear the temporary Buffer. */ + free (romBuffer); + + return result; +} + + + + +/******************************************************* + * This function is the Main Loop of the Emulator. + * Execute the commands. + * * TODO adresses: + * - INIT $8000 + * - IRQ $FFF0 + * - NMI $8082 +*/ +int emulator_loop (int debug) +{ + int result = 0; + SDL_Event event; + uint8_t opcode; + + emul.debugger.use = debug; + + /* Reset the Machine. */ + result = cpuReset (&emul.cpu); + if (result != 0) { + fprintf (stderr, "Impossible to reset the CPU.\n"); + return -1; + } + + while (emul.quit != 0) { + + /* BEGIN Critical Section. */ + if (debug == 1) { + SDL_mutexP (emul.debugger.mutexDebugger); + + /* If we put a break point. */ + if ((emul.debugger.debugExec == MANY_OPS) && + (emul.debugger.breakPoint == emul.cpu.pc)){ + emul.debugger.debugExec = 0; + } + + if (emul.debugger.debugExec > 0) { + /* Manage the Current Opcode. */ + opcode = emul.cpu.memRead (emul.cpu.pc); + result = cpu6502_execOpCode (&emul.cpu, opcode); + if (result != 0) { + + return -1; + } + + if (debug == 1) { + printRegs (&emul.cpu); + } + + /* Compute the CPU Time taken by the executed opcode. */ + emul.cpu.nbCycles -= OpcodesCycles[opcode]; + } + if (emul.debugger.debugExec == ONLY_ONE_OP) { + emul.debugger.debugExec = 0; + } + + /* END Critical Section. */ + SDL_mutexV (emul.debugger.mutexDebugger); + } + else { + + /* Manage the Current Opcode. */ + opcode = memory_fetch (emul.cpu.pc); + result = cpu6502_execOpCode (&emul.cpu, opcode); + if (result != 0) { + return -1; + } + + DEBUG_REGS(&emul.cpu); + + /* Compute the CPU Time taken by the executed opcode. */ + emul.cpu.nbCycles -= OpcodesCycles[opcode]; + } + + if (emul.cpu.nbCycles <= 0) { + DEBUG2 (("1 ligne.(%d)\n", emul.nbCycles)); + emul.cpu.nbCycles += NB_CYCLES_MAX; + emul.nbLines++; + if (emul.nbLines == 40) { + emul.ppu.spriteHit = 0x40; + } + if (emul.nbLines == NES_HEIGHT) { + /* We are now in the VBLANK. */ + /* Change the Status of the */ + bitsetPPUStatus (7, 1); + + /* Before Launch the NMI. we Redraw the Screen. */ + PPU_RedrawNesScreen (); + + /* Launch NMI */ + NMI_Interrupt (&emul.cpu); + + } + if (emul.nbLines == (NES_HEIGHT + NB_LINES_VBLANK)) { + /* VBLANK is finish, we restart at the First line. */ + emul.nbLines = 0; + emul.ppu.spriteHit = 0; + bitsetPPUStatus (7, 0); + } + } + + /* Manage the SDL Event. */ + while (SDL_PollEvent (&event)) { + HandleEvent (&event); + } + } + + /* Quit the SDL program. */ + SDL_Quit(); + + DEBUG0 (("quit: %d\n", emul.quit)); + return result; +} + + +/******************************************************* + * This function is the init function of the Window. + */ +int Window_Init () +{ + int result, i; + SDL_Color colors[256]; + + result = SDL_Init (SDL_INIT_TIMER|SDL_INIT_AUDIO|SDL_INIT_VIDEO); + if (result != 0) { + fprintf (stderr, "Impossible to Init Window.\n"); + return -1; + } + + /* Set video mode */ + emul.ppu.screen = SDL_SetVideoMode (NES_WIDTH, NES_HEIGHT, 8, SDL_SWSURFACE); + if (! emul.ppu.screen) { + fprintf (stderr, "Couldn't set %dx%d video mode: %s\n", + NES_WIDTH, NES_HEIGHT, SDL_GetError()); + return -2; + } + + /* Init the Palette of the Emulator. */ + for (i=0; i < 256; i++) { + /* Step1: Init the Palette.*/ + colors[i].r=0; + colors[i].g=0; + colors[i].b=0; + } + + for (i=0; i < 64; i++) { + /* Step1: Init the Palette.*/ + colors[i].r=nes_palette[i].r; + colors[i].g=nes_palette[i].g; + colors[i].b=nes_palette[i].b; + } + + /* Set palette */ + SDL_SetPalette(emul.ppu.screen, SDL_LOGPAL|SDL_PHYSPAL, colors, 0, 256); + + return 0; +} + +/******************************************************* + * This function is the Main SDL Event function. + */ +int HandleEvent (SDL_Event *event) +{ + + switch (event->type) { + + case SDL_KEYDOWN: + /* Manage the different keys. */ + switch (event->key.keysym.sym) { + + case SDLK_ESCAPE: + emul.quit = 0; + break; + case SDLK_UP: + DEBUG0 (("UP pressed.\n")); + emul.Pad1.keys [KEY_UP] = 1; + break; + case SDLK_DOWN: + DEBUG0 (("DOWN pressed.\n")); + emul.Pad1.keys [KEY_DOWN] = 1; + break; + case SDLK_RIGHT: + DEBUG0 (("RIGHT pressed.\n")); + emul.Pad1.keys [KEY_RIGHT] = 1; + break; + case SDLK_LEFT: + DEBUG0 (("LEFT pressed.\n")); + emul.Pad1.keys [KEY_LEFT] = 1; + break; + case SDLK_LCTRL: + DEBUG0 (("LEFT CONTROL pressed.\n")); + emul.Pad1.keys [KEY_A] = 1; + break; + case SDLK_LALT: + DEBUG0 (("LEFT ALT pressed.\n")); + emul.Pad1.keys [KEY_B] = 1; + break; + case SDLK_RETURN: + DEBUG0 (("RETURN pressed.\n")); + emul.Pad1.keys [KEY_START] = 1; + break; + case SDLK_BACKSPACE: + DEBUG0 (("BACKSPACE pressed.\n")); + emul.Pad1.keys [KEY_SELECT] = 1; + break; + } + break; + case SDL_KEYUP: + /* Manage the different keys. */ + switch (event->key.keysym.sym) { + + case SDLK_UP: + DEBUG0 (("UP UnPressed.\n")); + emul.Pad1.keys [KEY_UP] = 0; + break; + case SDLK_DOWN: + DEBUG0 (("DOWN UnPressed.\n")); + emul.Pad1.keys [KEY_DOWN] = 0; + break; + case SDLK_RIGHT: + DEBUG0 (("RIGHT UnPressed.\n")); + emul.Pad1.keys [KEY_RIGHT] = 0; + break; + case SDLK_LEFT: + DEBUG0 (("LEFT UnPressed.\n")); + emul.Pad1.keys [KEY_LEFT] = 0; + break; + case SDLK_LCTRL: + DEBUG0 (("LEFT CONTROL UnPressed.\n")); + emul.Pad1.keys [KEY_A] = 0; + break; + case SDLK_LALT: + DEBUG0 (("LEFT ALT UnPressed.\n")); + emul.Pad1.keys [KEY_B] = 0; + break; + case SDLK_RETURN: + DEBUG0 (("RETURN UnPressed.\n")); + emul.Pad1.keys [KEY_START] = 0; + break; + case SDLK_BACKSPACE: + DEBUG0 (("BACKSPACE UnPressed.\n")); + emul.Pad1.keys [KEY_SELECT] = 0; + break; + } + break; + case SDL_QUIT: + emul.quit = 0; + break; + default: + break; + } + + return 0; +} diff --git a/src/emulator/emulator.h b/src/emulator/emulator.h new file mode 100644 index 0000000..545c65b --- /dev/null +++ b/src/emulator/emulator.h @@ -0,0 +1,49 @@ +/*---------------------------------------------------------------------------- + * emulator.h. Emulator Object structure. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + + +#ifndef _EMULATOR_H +#define _EMULATOR_H + +/* Number of cycle to make a complete line. */ +#define NB_CYCLES_MAX 140 + +/* Number of line for the VBLANK. */ +#define NB_LINES_VBLANK 70 + +typedef struct nes_emulator_t { + /* Memory. */ + nes_memory_t memory; + /* CPU. */ + nes_cpu6502_t cpu; + /* PPU. */ + nes_ppu_t ppu; + /* APU */ + nes_apu_t apu; + + /* Debugger. */ + debugger_t debugger; + + /* Paddles. */ + paddle_t Pad1; + paddle_t Pad2; + + /* Counter of Lines to know where we are. */ + int16_t nbLines; + + /* Boolean to quit the emulator. */ + uint8_t quit; +}nes_emulator_t; + + +int SDLCALL SDLEventLoop (void *data); + +#endif diff --git a/src/emulator/memory.c b/src/emulator/memory.c new file mode 100644 index 0000000..9f72fff --- /dev/null +++ b/src/emulator/memory.c @@ -0,0 +1,259 @@ +/*---------------------------------------------------------------------------- + * memory.c. Main function to manage memory. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#include +#include +#include /* for exit */ + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "main.h" + +#include "debug.h" + +/******************************************************* + * Init the Memory structure. +*/ +int memory_init () +{ + int result = 0; + int i; + + for (i = 0; i < MEMORY_RAM_SIZE; i++) { + emul.memory.segment1 [i] = 0; + } + + //emul.memory + + return result; +} + +/******************************************************* + * This function read a 16bits and return it. +*/ +uint16_t memory_Read16 (uint16_t hight, uint16_t low) +{ + uint16_t read_value; + /* Step1 detect the memory zone we want to access. */ + if (hight > MEMORY_PROGROM) { + DEBUG2 (("Access PROG ROM.\n")); + /* -Low part. */ + read_value = emul.memory.prgRom [low - MEMORY_PROGROM]; + /* -Hight part. */ + read_value |= emul.memory.prgRom [hight - MEMORY_PROGROM] << 8; + + return read_value; + } + else if (hight > MEMORY_SAVESLOT_2) { + DEBUG0 (("%d)TODO Access to Save Slot 2.\n", __LINE__)); + exit (1); + } + else if (hight > MEMORY_SAVESLOT_1) { + DEBUG0 (("%d)Access to Save Slot 1.\n", __LINE__)); + exit (1); + } + else if (hight > MEMORY_APU_INPUT) { + DEBUG0 (("%d)Access to APU Input.\n", __LINE__)); + exit (1); + } + else if (hight > MEMORY_PPU_REG) { + DEBUG0 (("%d)Access to PPU Reg.\n", __LINE__)); + exit (1); + } + else if (hight > MEMORY_RAM) { + DEBUG0 (("%d)Access to Ram.(0x%x)\n", __LINE__, hight)); + exit (1); + } + else { + DEBUG2 (("Impossible to access to this Memory: 0x%x.\n", hight)); + } + return 0; +} + +/******************************************************* + * This function return the opcode to do. +*/ +uint8_t memory_fetch (uint16_t addr) +{ + if (addr < MEMORY_PROGROM) { + return memory_Read (addr); + } + else { + return emul.memory.prgRom [addr - MEMORY_PROGROM]; + } +} + +/******************************************************* + * This function read the memory. +*/ +uint8_t memory_Read (uint16_t addr) +{ + if (addr >= MEMORY_PROGROM) { + DEBUG2 (("Access PROG ROM.\n")); + return emul.memory.prgRom [addr - MEMORY_PROGROM]; + } + else if (addr >= MEMORY_SAVESLOT_2) { + DEBUG0 (("%d)TODO Access to Save Slot 2.\n", __LINE__)); + exit (1); + } + else if (addr >= MEMORY_SAVESLOT_1) { + DEBUG0 (("%d)TODO Access to Save Slot 1.\n", __LINE__)); + exit (1); + } + else if (addr >= MEMORY_APU_INPUT) { + DEBUG2 (("Access to APU Input (%d).\n", (addr - MEMORY_APU_INPUT))); + + switch (addr) { + + case 0x4016: + return paddle_Read (&emul.Pad1); + break; + case 0x4017: + return paddle_Read (&emul.Pad2); + break; + default: + return emul.apu.registers[addr - MEMORY_APU_INPUT]; + } + } + else if (addr >= MEMORY_PPU_REG) { + DEBUG2 (("Access to PPU Reg.\n", __LINE__)); + return memory_Read_PPu (addr); + } + else { + /* if (addr >= MEMORY_RAM) */ + DEBUG2 (("%d)Access to Ram.(0x%x)\n", __LINE__, addr)); + if (addr > 0x800) { + DEBUG0 (("TODO Access ghost RAM.(0x%x)\n", addr)); + exit (1); + } + + return emul.memory.segment1 [addr]; + } + + return 0; +} + +/******************************************************* + * This function write the memory. +*/ +void memory_Write (uint16_t addr, uint8_t value) +{ + + if (addr < MEMORY_PPU_REG) { + DEBUG2 (("Access to Ram.(0x%x)\n", addr)); + + emul.memory.segment1 [(addr & 0x7FF)] = value; + DEBUG2 (("On viend d'enregistrer a %x = %x\n", (addr & 0x7FF), value)); + } + else if (addr < MEMORY_APU_INPUT) { + DEBUG2 (("Access to PPU Reg.\n")); + + memory_Write_PPu (addr, value); + } + else if (addr < MEMORY_SAVESLOT_1) { + switch (addr) { + + case 0x4014: + /* Dma Access to the Sprite memory. */ + PPU_DMA_SpriteCopy (value); + break; + case 0x4016: + paddle_Write (&emul.Pad1, value); + break; + case 0x4017: + paddle_Write (&emul.Pad2, value); + break; + default: + fprintf (stdout, "APU input unknown: %d\n", addr); + } + + DEBUG2 (("Access to APU Input.\n")); + DEBUG2 (("APU Save at %d.\n", (addr - MEMORY_APU_INPUT) )); + emul.apu.registers[addr - MEMORY_APU_INPUT] = value; + } + else if (addr < MEMORY_SAVESLOT_2) { + DEBUG0 (("TODO Access to Save Slot 1.\n")); + exit (1); + } + else if (addr < MEMORY_PROGROM) { + DEBUG0 (("TODO Access to Save Slot 2.\n")); + exit (1); + } + else { + DEBUG0 (("Impossible to write to this Memory: 0x%x.\n", addr)); + } +} + +/******************************************************* + * This function read the memory in the PAGE 0. +*/ +uint8_t memory_ReadIndirectIndexed (uint8_t addr) +{ + return emul.memory.segment1 [MEMORY_INDIRECT_INDEXED_START + addr]; +} + + +/******************************************************* + * This function write the memory in the PAGE 0. +*/ +void memory_WriteIndirectIndexed (uint8_t addr, uint8_t value) +{ + emul.memory.segment1 [MEMORY_INDIRECT_INDEXED_START + addr] = value; + DEBUG2 (("WII, On viend d'enregistrer a %x = %d\n", + (MEMORY_INDIRECT_INDEXED_START + addr), value)); + //DumpMemory (); +} + +/******************************************************* + * Dump Memory. +*/ +void DumpMemory (uint16_t StartAddr) +{ + int i; + uint16_t cpt = 0; + int quit = 0; + fprintf (stderr, "startAddr: %x\n", StartAddr); + /* Sanity checks. */ + if (StartAddr > 0x800) { + fprintf (stderr, "Impossible to Dump this adress (0x%x). Out of Range.\n"); + return; + } + + cpt = StartAddr; + + while (quit == 0) { + + fprintf (stdout, "%4.4x:", cpt); + for (i = 0; i < 16; i++) { + if (cpt >= MEMORY_RAM_SIZE) { + /* We are arrived at the end of the RAM. */ + quit = 1; + break; + } + if (emul.memory.segment1[cpt] != 0) { + fprintf (stdout, " \033[32m%2.2x\033[0m", emul.memory.segment1[cpt]); + } + else { + fprintf (stdout, " %2.2x", emul.memory.segment1[cpt]); + } + + cpt++; + } + fprintf (stdout, "\n"); + } +} diff --git a/src/emulator/memory.h b/src/emulator/memory.h new file mode 100644 index 0000000..061424c --- /dev/null +++ b/src/emulator/memory.h @@ -0,0 +1,56 @@ +/*---------------------------------------------------------------------------- + * memory.h. memory structure. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __MEMORY_H +#define __MEMORY_H + + +/* + * Memory Map: + * ========== + * +----------+-------+-------+----------------------+ + * | Address | End | Size | Description | + * +----------+-------+-------+----------------------+ + * | $0000 | $1FFF | $0800 | Ram | + * | $2000 | $3FFF | $0008 | PPU Register | + * | $4000 | $4017 | $0018 | APU & Input Register | + * | $4018 | $5777 | $1FE8 | Written to cart * 1 | + * | $6000 | $7FFF | $2000 | Written to cart * 2 | + * | $8000 | $FFFF | $8000 | Program Rom * 2 | + * +----------+-------+-------+----------------------+ + * + */ + +#define MEMORY_RAM 0x0000 +#define MEMORY_PPU_REG 0x2000 +#define MEMORY_APU_INPUT 0x4000 +#define MEMORY_SAVESLOT_1 0x4018 +#define MEMORY_SAVESLOT_2 0x6000 +#define MEMORY_PROGROM 0x8000 + +#define MEMORY_INDIRECT_INDEXED_START 0x00aa + +#define MEMORY_STACK_INDEX_START 0x100 + +#define MEMORY_RAM_SIZE 2048 +#define MEMORY_PROGROM_SIZE 32768 + +typedef struct nes_memory_t { + /* OOO - 0x800 */ + unsigned char segment1[MEMORY_RAM_SIZE]; + + /* Prg-ROM */ + unsigned char *prgRom; + +}nes_memory_t; + + +#endif diff --git a/src/emulator/nespal.h b/src/emulator/nespal.h new file mode 100644 index 0000000..f5ae019 --- /dev/null +++ b/src/emulator/nespal.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * nespal.h. Contain the complete nes palette. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __NESPAL_H +#define __NESPAL_H + + +typedef struct nescol_t { + uint8_t r; + uint8_t g; + uint8_t b; +}nescol_t; + + +nescol_t nes_palette[64] = +{ + {0x80,0x80,0x80}, {0x00,0x00,0xBB}, {0x37,0x00,0xBF}, {0x84,0x00,0xA6}, + {0xBB,0x00,0x6A}, {0xB7,0x00,0x1E}, {0xB3,0x00,0x00}, {0x91,0x26,0x00}, + {0x7B,0x2B,0x00}, {0x00,0x3E,0x00}, {0x00,0x48,0x0D}, {0x00,0x3C,0x22}, + {0x00,0x2F,0x66}, {0x00,0x00,0x00}, {0x05,0x05,0x05}, {0x05,0x05,0x05}, + + {0xC8,0xC8,0xC8}, {0x00,0x59,0xFF}, {0x44,0x3C,0xFF}, {0xB7,0x33,0xCC}, + {0xFF,0x33,0xAA}, {0xFF,0x37,0x5E}, {0xFF,0x37,0x1A}, {0xD5,0x4B,0x00}, + {0xC4,0x62,0x00}, {0x3C,0x7B,0x00}, {0x1E,0x84,0x15}, {0x00,0x95,0x66}, + {0x00,0x84,0xC4}, {0x11,0x11,0x11}, {0x09,0x09,0x09}, {0x09,0x09,0x09}, + + {0xFF,0xFF,0xFF}, {0x00,0x95,0xFF}, {0x6F,0x84,0xFF}, {0xD5,0x6F,0xFF}, + {0xFF,0x77,0xCC}, {0xFF,0x6F,0x99}, {0xFF,0x7B,0x59}, {0xFF,0x91,0x5F}, + {0xFF,0xA2,0x33}, {0xA6,0xBF,0x00}, {0x51,0xD9,0x6A}, {0x4D,0xD5,0xAE}, + {0x00,0xD9,0xFF}, {0x66,0x66,0x66}, {0x0D,0x0D,0x0D}, {0x0D,0x0D,0x0D}, + + {0xFF,0xFF,0xFF}, {0x84,0xBF,0xFF}, {0xBB,0xBB,0xFF}, {0xD0,0xBB,0xFF}, + {0xFF,0xBF,0xEA}, {0xFF,0xBF,0xCC}, {0xFF,0xC4,0xB7}, {0xFF,0xCC,0xAE}, + {0xFF,0xD9,0xA2}, {0xCC,0xE1,0x99}, {0xAE,0xEE,0xB7}, {0xAA,0xF7,0xEE}, + {0xB3,0xEE,0xFF}, {0xDD,0xDD,0xDD}, {0x11,0x11,0x11}, {0x11,0x11,0x11} +}; + +#endif diff --git a/src/emulator/paddle.c b/src/emulator/paddle.c new file mode 100644 index 0000000..331e69f --- /dev/null +++ b/src/emulator/paddle.c @@ -0,0 +1,81 @@ +/*---------------------------------------------------------------------------- + * paddle.c. Paddle Manager. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 20/03/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + + +#include +#include + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "main.h" + +#include "debug.h" + + + +/******************************************************* + * Init the paddle structure. + */ +int paddle_Init (paddle_t *paddle) +{ + int i; + + paddle->lastWrite = 0; + paddle->CurrentPosition = 1; + + for (i = 0; i < PADDLE_NB_KEYS; i++) { + paddle->keys[i] = 0; + } + + return 0; +} + + +/******************************************************* + * Read the Paddle Value. + */ +int paddle_Read (paddle_t *paddle) +{ + int result = 0x40; + + if (paddle->keys[paddle->CurrentPosition] == 1) { + result = 0x41; + } + + if (paddle->CurrentPosition == PADDLE_NB_KEYS) { + paddle->CurrentPosition = 1; + } + else { + paddle->CurrentPosition++; + } + + return result; +} + +/******************************************************* + * Write the Paddle Value. + */ +void paddle_Write (paddle_t *paddle, uint8_t value) +{ + if ((paddle->lastWrite == 1) && (value == 0)) { + paddle_Init (paddle); + } + + paddle->lastWrite = value; +} + diff --git a/src/emulator/paddle.h b/src/emulator/paddle.h new file mode 100644 index 0000000..fedc9a3 --- /dev/null +++ b/src/emulator/paddle.h @@ -0,0 +1,39 @@ +/*---------------------------------------------------------------------------- + * paddle.h. Paddle Manager. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 20/03/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef _PADDLE_H +#define _PADDLE_H + + +#define PADDLE_NB_KEYS 24 + +#define KEY_A 1 +#define KEY_B 2 +#define KEY_SELECT 3 +#define KEY_START 4 +#define KEY_UP 5 +#define KEY_DOWN 6 +#define KEY_LEFT 7 +#define KEY_RIGHT 8 + + +/* Structure of the Paddle. */ +typedef struct paddle_t { + + uint8_t lastWrite; + uint8_t CurrentPosition; + + uint8_t keys[PADDLE_NB_KEYS]; + +} paddle_t; + + +#endif /* _PADDLE_H */ diff --git a/src/emulator/ppu.c b/src/emulator/ppu.c new file mode 100644 index 0000000..2d1e3d7 --- /dev/null +++ b/src/emulator/ppu.c @@ -0,0 +1,442 @@ +/*---------------------------------------------------------------------------- + * ppu.c. Main Picture Processor. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + + +#include +#include + +#include + +#include "memory.h" +#include "cpu6502.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "ppu_tiles.h" +#include "main.h" + +#include "debug.h" + + +/******************************************************* + * Init the PPU structure. +*/ +int ppu_init () +{ + int result = 0; + + emul.ppu.init = 0; + + + /* Init the 8 registers. */ + /* ==================== */ + + /* PPU Control Register 1. */ + emul.ppu.registers.ControlRegister1 = 0; + /* PPU Control Register 2. */ + emul.ppu.registers.ControlRegister2 = 0; + /* PPU Status Register. */ + emul.ppu.registers.StatusRegister = 0; + /* PPU Screen Scroll Offset. */ + emul.ppu.registers.ScreenScrollOffset = 0; + + /* PPU Memory Address. */ + emul.ppu.registers.PPUMemAddress = 0; + emul.ppu.registers.accessPPUMem = ACCESS_HIGH; + + /* PPU Sprite Memory Address. */ + emul.ppu.registers.SpriteMemAddress = 0; + + return result; +} + +/******************************************************* + * This function read the Vram. + */ +uint8_t PPU_Read_Vram (uint16_t addr) +{ + /* Plage of the Memory Space. */ + addr &= 0x3FFF; + + if ((addr & 0xFF00) == 0x3F00) { + return emul.ppu.vram [(addr & 0xFF1F)]; + } + else { + return emul.ppu.vram [addr]; + } +} + +/******************************************************* + * This function write the Vram. + */ +void PPU_Write_Vram (uint16_t addr, uint8_t value) +{ + /* Plage of the Memory Space. */ + addr &= 0x3FFF; + + /* If we write the first element of the palette, we mirrored it to the + * both palette. */ + if ((addr & 0xFF00) == 0x3F00) { + /* Palette. */ + + if ((addr == SPRITE_PALETTE) || (addr == PICTURE_PALETTE)) { + emul.ppu.vram[SPRITE_PALETTE] = value; + emul.ppu.vram[PICTURE_PALETTE] = value; + } + else { + emul.ppu.vram[(addr & 0xFF1F)] = value; + } + } + else { + emul.ppu.vram[addr] = value; + } +} + + +/******************************************************* + * This function read Register Value +*/ +uint8_t memory_Read_PPu (uint16_t addr) +{ + uint8_t result = 0; + DEBUG2 (("%s: %x\n", __FUNCTION__, addr)); + + switch (addr) { + + case 0x2000: + /* PPU Control Register 1 */ + result = emul.ppu.registers.ControlRegister1; + break; + case 0x2001: + /* PPU Control Register 2 */ + result = emul.ppu.registers.ControlRegister2; + break; + case 0x2002: + /* PPU Status Register */ + result = emul.ppu.registers.StatusRegister | emul.ppu.spriteHit; + emul.ppu.registers.StatusRegister = 0; + emul.ppu.registers.PPUMemAddress = ACCESS_HIGH; + break; + case 0x2004: + /* Sprite Memory Data */ + result = emul.ppu.sprite_ram [emul.ppu.registers.SpriteMemAddress]; + break; + case 0x2007: + /* PPU memory Data */ + /* Return the last value readed. The first time the value is unknown. */ + + if (emul.ppu.registers.PPUMemAddress < PICTURE_PALETTE) { + result = emul.ppu.PPU_transfert; + emul.ppu.PPU_transfert = PPU_Read_Vram (emul.ppu.registers.PPUMemAddress); + } + else { + result = PPU_Read_Vram (emul.ppu.registers.PPUMemAddress); + emul.ppu.PPU_transfert = PPU_Read_Vram + ((emul.ppu.registers.PPUMemAddress & 0x00FF) | 0x2F00); + } + + + if ((emul.ppu.registers.PPUMemAddress >= PATTERN_TABLE_1) && + (emul.ppu.registers.PPUMemAddress < NAME_TABLE_0)) { + fprintf (stdout, "Read 2007:%x=%x\n", emul.ppu.registers.PPUMemAddress, + result); + } + + /* And Increment the mem Address pointer. */ + if (emul.ppu.registers.ControlRegister1 & CONTROL_INC) { + emul.ppu.registers.PPUMemAddress += 32; + } + else { + emul.ppu.registers.PPUMemAddress++; + } + break; + default: + DEBUG0 (("Impossible to read at this address (0x%x)\n", addr)); + } + + return result; +} + +/******************************************************* + * This function read Register Value +*/ +void memory_Write_PPu (uint16_t addr, uint8_t value) +{ + DEBUG2 (("%s:0x%x=0x%x\n", __FUNCTION__, addr, value)); + + switch (addr) { + + case 0x2000: + /* PPU Control Register 1 */ + emul.ppu.registers.ControlRegister1 = value; + fprintf (stdout, "Ecriture 2000 register1: $%x\n", + emul.ppu.registers.ControlRegister1); + break; + case 0x2001: + /* PPU Control Register 2 */ + emul.ppu.registers.ControlRegister2 = value; + break; + case 0x2003: + /* Sprite Memory Address */ + emul.ppu.registers.SpriteMemAddress = value; + break; + case 0x2004: + /* Sprite Memory Data */ + emul.ppu.sprite_ram [emul.ppu.registers.SpriteMemAddress] = value; + emul.ppu.registers.SpriteMemAddress++; + break; + case 0x2005: + /* Screen Scroll Offset */ + DEBUG0 (("TODO: Write PPU reg: 0x2005\n")); + + emul.ppu.registers.accessPPUMem = !emul.ppu.registers.accessPPUMem; + //TODO exit (1); + break; + case 0x2006: + /* PPU memory Address */ + if (emul.ppu.registers.accessPPUMem) { + emul.ppu.registers.PPUMemAddress = + (emul.ppu.registers.PPUMemAddress & 0xFF) | (value << 8); + } + else { + emul.ppu.registers.PPUMemAddress = + (emul.ppu.registers.PPUMemAddress & 0xFF00) | (value & 0xFF); + } +#if 0 + fprintf (stdout, "Ecriture 2006: %x, value: %x\n", + emul.ppu.registers.PPUMemAddress, value); +#endif + /* Change it. */ + emul.ppu.registers.accessPPUMem = !emul.ppu.registers.accessPPUMem; + DEBUG2 (("Address of the address PPU addr pointer: 0x%x, value: %x\n", + emul.ppu.registers.PPUMemAddress, value)); + break; + case 0x2007: + /* PPU memory Data */ + DEBUG0 (("2007 - save [0x%x]=0x%x\n", emul.ppu.registers.PPUMemAddress, + value)); + PPU_Write_Vram (emul.ppu.registers.PPUMemAddress, value); + if (emul.ppu.registers.ControlRegister1 & CONTROL_INC) { + emul.ppu.registers.PPUMemAddress += 32; + } + else { + emul.ppu.registers.PPUMemAddress++; + } + break; + default: + DEBUG0 (("Impossible to read at this address (0x%x)\n" + "we stop the Emulator.\n ", addr)); + exit (0); + } +} + +/******************************************************* + * This function Draw a pixel on the Screen. + */ +void DrawPixel (SDL_Surface *screen, int x, int y, Uint8 color) +{ + Uint8 *bufp; + + /* Get the address of the Pixel. */ + bufp = (Uint8 *)screen->pixels + y*screen->pitch + x; + /* Write the Color. */ + *bufp = color; +} + +/******************************************************* + * This function Draw a Tile on the Screen. +*/ +void DrawTile (uint8_t x, uint8_t y, uint16_t StartTile, uint8_t startX, + uint16_t BGpatternAddr) +{ + uint8_t *pData1, *pData2; + uint8_t color, attr; + uint16_t numTile; + int i, j, px, py; + + pData1 = &emul.ppu.vram [StartTile]; + pData2 = &emul.ppu.vram [StartTile + 8]; + DEBUG2 (("DrawTile x: %d, y:%d\n", x, y)); + + /* Get the Num Tile. */ + numTile = (y * NES_TILES_WIDTH) + x; + + /* Get the Attribute for this Tile. */ + attr = (emul.ppu.vram[BGpatternAddr + attr_tiles[numTile].square] + >> attr_tiles[numTile].shift) & 0x03; + + /* For all the line of the tile. */ + for (j = 0; j < 8; j++) { + DEBUG2 (("(%d)Depart: %d et %d\n", StartTile, *pData1, *pData2)); + /* For all the Column of the tile. */ + for (i = startX; i < 8; i++) { + /* bit1: Fill Hight part.*/ + color = ((*pData2 >> (7-i)) & 0x1) << 1; + /* bit0: Fill Low part.*/ + color |= ((*pData1 >> (7-i)) & 0x1); + if (color != 0) { + /* bit2-3: */ + color |= (attr << 2); + color = PPU_Read_Vram (PICTURE_PALETTE + color); + + px = (x * 8) + i; + py = (y * 8) + j; + + DEBUG2 (("color makup: hight: %d, low: %d = color: %d (x:%d,y:%d)\n", + ((*pData2 >> (7-i)) & 0x1), ((*pData1 >> (7-i)) & 0x1), color, + px, py)); + + DrawPixel (emul.ppu.screen, px, py, color); + } + } + pData1++; + pData2++; + } +} + + +/******************************************************* + * This function redraw the Screen. +*/ +void PPU_RedrawNesScreen () +{ + int x, y; + uint16_t pTileArea, screenPatAddr, BGpatternAddr; + uint8_t value; + DEBUG2 (("%s\n", __FUNCTION__)); + + /* Clear the Screen. */ + SDL_FillRect (emul.ppu.screen, 0, emul.ppu.vram[PICTURE_PALETTE]); + + //emul.ppu.registers.StatusRegister = 0; + if ((emul.ppu.registers.ControlRegister1 & CONTROL_TAB_ADDR) == 0) { + pTileArea = PAGE0; + BGpatternAddr = ATTRIBUTE_TABLE_0; + } + else if ((emul.ppu.registers.ControlRegister1 & CONTROL_TAB_ADDR) == 1) { + pTileArea = PAGE1; + BGpatternAddr = ATTRIBUTE_TABLE_1; + } + else if ((emul.ppu.registers.ControlRegister1 & CONTROL_TAB_ADDR) == 2) { + pTileArea = PAGE2; + BGpatternAddr = ATTRIBUTE_TABLE_2; + } + else { + pTileArea = PAGE3; + BGpatternAddr = ATTRIBUTE_TABLE_3; + } + + if (emul.ppu.registers.ControlRegister1 & CONTROL_SCREEN_PATT_ADDR) { + screenPatAddr = 0x1000; + } + else { + screenPatAddr = 0; + } + + /* Boucle to draw. */ + for (y = 0; y < NES_TILES_HEIGHT; y++) { + for (x = 0; x < NES_TILES_WIDTH; x++) { + value = emul.ppu.vram [pTileArea++]; + DEBUG2 (("On veut le tile: %x\n", value)); + DrawTile (x, y, ((value * 16) + screenPatAddr), 0, BGpatternAddr); + } + } + + /* Then Update the Screen */ + SDL_UpdateRect(emul.ppu.screen, 0, 0, NES_WIDTH, NES_HEIGHT); + + //emul.ppu.registers.StatusRegister = 0x80; +} + + +/******************************************************* + * Change One Bit of the PPU status. +*/ +void bitsetPPUStatus (uint8_t flag, uint8_t val) +{ + if (val == 0) { + emul.ppu.registers.StatusRegister &= ~(1 << flag); + } + else { + emul.ppu.registers.StatusRegister |= (1 << flag); + } +} + +/******************************************************* + * This function Show the Tiles in Rom. + */ +void PPU_ShowTiles (int page) +{ + int x, y; + uint16_t screenPatAddr; + uint8_t value; + uint16_t BGpatternAddr; + + fprintf (stdout, "Print the Tile Page: %d\n", page); + + /* Set the Start address of the Tiles area. */ + if (page == 1) { + screenPatAddr = 0x1000; + } + else { + screenPatAddr = 0; + } + + value = 0; + + /* Boucle to draw. */ + for (y = 0; y < NES_TILES_HEIGHT/2; y++) { + for (x = 0; x < (NES_TILES_WIDTH/2) + 1; x++) { + + DEBUG2 (("On veut le tile: %x (%d,%d)\n", value, x, y)); + DrawTile (x, y, ((value * 16) + screenPatAddr), 0, BGpatternAddr); + value++; + } + } + + /* Then Update the Screen*/ + SDL_UpdateRect (emul.ppu.screen, 0, 0, NES_WIDTH, NES_HEIGHT); +} + +/******************************************************* + * This function Clear the Screen. + */ +void PPU_ClearScreen () +{ + SDL_FillRect (emul.ppu.screen, 0, emul.ppu.vram[PICTURE_PALETTE]); + + /* Then Update the Screen*/ + SDL_UpdateRect (emul.ppu.screen, 0, 0, NES_WIDTH, NES_HEIGHT); +} + + +/******************************************************* + * This function Clear the Screen. + */ +void PPU_DMA_SpriteCopy (uint8_t value) +{ + int i; + uint16_t cpt; + uint16_t addr; + + cpt = emul.ppu.registers.SpriteMemAddress; + addr = 0x100 * value; + + for (i=0; i < 0x100; i++) { + if (cpt == SPRITE_RAM_SIZE) { + cpt = 0; + } + /* Copy */ + emul.ppu.sprite_ram [cpt++] = memory_Read (addr++); + } +} diff --git a/src/emulator/ppu.h b/src/emulator/ppu.h new file mode 100644 index 0000000..af26658 --- /dev/null +++ b/src/emulator/ppu.h @@ -0,0 +1,130 @@ +/*---------------------------------------------------------------------------- + * ppu.h. ppu structure. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __PPU_H +#define __PPU_H + +#define PAL_NMI_TICK 20 + +#define VRAM_SIZE 16384 + +#define SPRITE_RAM_SIZE 256 + +/* + * Memory Map of the VRAM: + * ====================== + * + * +----------+-------+-------+----------------------+ + * | Address | End | Size | Description | + * +----------+-------+-------+----------------------+ + * | $0000 | $0FFF | $1000 | Pattern Table #0 | + * +----------+-------+-------+----------------------+ + * | $1000 | $1FFF | $1000 | Pattern Table #1 | + * +----------+-------+-------+----------------------+ + * | $2000 | $23BF | $3C0 | Name Table #0 | + * +----------+-------+-------+----------------------+ + * | $23C0 | $23FF | $40 | Attribute Table #0 | + * +----------+-------+-------+----------------------+ + * | $2400 | $27BF | $3C0 | Name Table #1 | + * +----------+-------+-------+----------------------+ + * | $27C0 | $27FF | $40 | Attribute Table #1 | + * +----------+-------+-------+----------------------+ + * | $2800 | $2BBF | $3C0 | Name Table #2 | + * +----------+-------+-------+----------------------+ + * | $2BC0 | $2BFF | $40 | Attribute Table #2 | + * +----------+-------+-------+----------------------+ + * | $2C00 | $2FBF | $3C0 | Name Table #2 | + * +----------+-------+-------+----------------------+ + * | $2FC0 | $2FFF | $40 | Attribute Table #2 | + * +----------+-------+-------+----------------------+ + * | $3000 | $3EFF | $EFF | Not Used | + * +----------+-------+-------+----------------------+ + * | $3F00 | $3F0F | $10 | Picture Palette | + * +----------+-------+-------+----------------------+ + * | $3F10 | $3F1F | $10 | Sprite Palette | + * +----------+-------+-------+----------------------+ + * | $3F20 | $3FFF | $E0 | Mirror of Palettes | + * +----------+-------+-------+----------------------+ + * + */ + +#define PATTERN_TABLE_0 0x0000 +#define PATTERN_TABLE_1 0x1000 +#define NAME_TABLE_0 0x2000 +#define ATTRIBUTE_TABLE_0 0x23C0 +#define NAME_TABLE_1 0x2400 +#define ATTRIBUTE_TABLE_1 0x27C0 +#define NAME_TABLE_2 0x2800 +#define ATTRIBUTE_TABLE_2 0x2BC0 +#define NAME_TABLE_3 0x2C00 +#define ATTRIBUTE_TABLE_3 0x2FC0 +#define PICTURE_PALETTE 0x3F00 +#define SPRITE_PALETTE 0x3F10 + + +#define PAGE0 0x2000 +#define PAGE1 0x2400 +#define PAGE2 0x2800 +#define PAGE3 0x2C00 + +#define NES_WIDTH 256 +#define NES_HEIGHT 240 + +#define NES_TILES_WIDTH 32 /* 256 / 8 */ +#define NES_TILES_HEIGHT 30 /* 240 / 8 */ + +#define ACCESS_HIGH 1 +#define ACCESS_LOW 0 + +#define CONTROL_INC 0x04 +#define CONTROL_BACKGROUND_PATTERN 0x08 +#define CONTROL_TAB_ADDR 0x03 +#define CONTROL_SCREEN_PATT_ADDR 0x016 + +typedef struct ppu_register_t { + /* PPU Control Register 1. */ + uint8_t ControlRegister1; + /* PPU Control Register 2. */ + uint8_t ControlRegister2; + /* PPU Status Register. */ + uint8_t StatusRegister; + /* PPU Screen Scroll Offset. */ + uint8_t ScreenScrollOffset; + /* PPU Tiles Address. */ + uint16_t PPUMemAddress; + uint8_t accessPPUMem; + + /* PPU Sprites Address. */ + uint8_t SpriteMemAddress; + +}ppu_register_t; + +typedef struct nes_ppu_t { + + ppu_register_t registers; + /* Kind of boolean to init or not the PPU. */ + uint8_t init; + /* Timer for the PPU's NMI (Non Maskable Interrupt */ + SDL_TimerID timerID; + /* Main Screen. */ + SDL_Surface *screen; + /* Temporary buffer to transfert PPU data. */ + uint8_t PPU_transfert; + /* Video Ram. */ + uint8_t vram [VRAM_SIZE]; + /* Sprite Ram. */ + uint8_t sprite_ram [SPRITE_RAM_SIZE]; + + uint8_t spriteHit; +}nes_ppu_t; + + +#endif diff --git a/src/emulator/ppu_tiles.h b/src/emulator/ppu_tiles.h new file mode 100644 index 0000000..ec72672 --- /dev/null +++ b/src/emulator/ppu_tiles.h @@ -0,0 +1,212 @@ +/*---------------------------------------------------------------------------- + * NES PPU: ppu_tiles.h. This file contain array for the link between the + * tile Number and the Square position. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 13/03/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef __PPU_TILES_H +#define __PPU_TILES_H + +typedef struct attr_elem_t { + uint8_t square; + uint8_t shift; +}attr_elem_t; + +#define E1 00 +#define E2 02 +#define E3 04 +#define E4 06 + +attr_elem_t attr_tiles[] = { + /* Line 1. */ + { 0,E1}, { 0,E1}, { 0,E2}, { 0,E2}, { 1,E1}, { 1,E1}, { 1,E2}, { 1,E2}, + { 2,E1}, { 2,E1}, { 2,E2}, { 2,E2}, { 3,E1}, { 3,E1}, { 3,E2}, { 3,E2}, + { 4,E1}, { 4,E1}, { 4,E2}, { 4,E2}, { 5,E1}, { 5,E1}, { 5,E2}, { 5,E2}, + { 6,E1}, { 6,E1}, { 6,E2}, { 6,E2}, { 7,E1}, { 7,E1}, { 7,E2}, { 7,E2}, + + /* Line 2. */ + { 0,E1}, { 0,E1}, { 0,E2}, { 0,E2}, { 1,E1}, { 1,E1}, { 1,E2}, { 1,E2}, + { 2,E1}, { 2,E1}, { 2,E2}, { 2,E2}, { 3,E1}, { 3,E1}, { 3,E2}, { 3,E2}, + { 4,E1}, { 4,E1}, { 4,E2}, { 4,E2}, { 5,E1}, { 5,E1}, { 5,E2}, { 5,E2}, + { 6,E1}, { 6,E1}, { 6,E2}, { 6,E2}, { 7,E1}, { 7,E1}, { 7,E2}, { 7,E2}, + + /* Line 3. */ + { 0,E3}, { 0,E3}, { 0,E4}, { 0,E4}, { 1,E3}, { 1,E3}, { 1,E4}, { 1,E4}, + { 2,E3}, { 2,E3}, { 2,E4}, { 2,E4}, { 3,E3}, { 3,E3}, { 3,E4}, { 3,E4}, + { 4,E3}, { 4,E3}, { 4,E4}, { 4,E4}, { 5,E3}, { 5,E3}, { 5,E4}, { 5,E4}, + { 6,E3}, { 6,E3}, { 6,E4}, { 6,E4}, { 7,E3}, { 7,E3}, { 7,E4}, { 7,E4}, + + /* Line 4. */ + { 0,E3}, { 0,E3}, { 0,E4}, { 0,E4}, { 1,E3}, { 1,E3}, { 1,E4}, { 1,E4}, + { 2,E3}, { 2,E3}, { 2,E4}, { 2,E4}, { 3,E3}, { 3,E3}, { 3,E4}, { 3,E4}, + { 4,E3}, { 4,E3}, { 4,E4}, { 4,E4}, { 5,E3}, { 5,E3}, { 5,E4}, { 5,E4}, + { 6,E3}, { 6,E3}, { 6,E4}, { 6,E4}, { 7,E3}, { 7,E3}, { 7,E4}, { 7,E4}, + + /* Line 5. */ + { 8,E1}, { 8,E1}, { 8,E2}, { 8,E2}, { 9,E1}, { 9,E1}, { 9,E2}, { 9,E2}, + {10,E1}, {10,E1}, {10,E2}, {10,E2}, {11,E1}, {11,E1}, {11,E2}, {11,E2}, + {12,E1}, {12,E1}, {12,E2}, {12,E2}, {13,E1}, {13,E1}, {13,E2}, {13,E2}, + {14,E1}, {14,E1}, {14,E2}, {14,E2}, {15,E1}, {15,E1}, {15,E2}, {15,E2}, + + /* Line 6. */ + { 8,E1}, { 8,E1}, { 8,E2}, { 8,E2}, { 9,E1}, { 9,E1}, { 9,E2}, { 9,E2}, + {10,E1}, {10,E1}, {10,E2}, {10,E2}, {11,E1}, {11,E1}, {11,E2}, {11,E2}, + {12,E1}, {12,E1}, {12,E2}, {12,E2}, {13,E1}, {13,E1}, {13,E2}, {13,E2}, + {14,E1}, {14,E1}, {14,E2}, {14,E2}, {15,E1}, {15,E1}, {15,E2}, {15,E2}, + + /* Line 7. */ + { 8,E3}, { 8,E3}, { 8,E4}, { 8,E4}, { 9,E3}, { 9,E3}, { 9,E4}, { 9,E4}, + {10,E3}, {10,E3}, {10,E4}, {10,E4}, {11,E3}, {11,E3}, {11,E4}, {11,E4}, + {12,E3}, {12,E3}, {12,E4}, {12,E4}, {13,E3}, {13,E3}, {13,E4}, {13,E4}, + {14,E3}, {14,E3}, {14,E4}, {14,E4}, {15,E3}, {15,E3}, {15,E4}, {15,E4}, + + /* Line 8. */ + { 8,E3}, { 8,E3}, { 8,E4}, { 8,E4}, { 9,E3}, { 9,E3}, { 9,E4}, { 9,E4}, + {10,E3}, {10,E3}, {10,E4}, {10,E4}, {11,E3}, {11,E3}, {11,E4}, {11,E4}, + {12,E3}, {12,E3}, {12,E4}, {12,E4}, {13,E3}, {13,E3}, {13,E4}, {13,E4}, + {14,E3}, {14,E3}, {14,E4}, {14,E4}, {15,E3}, {15,E3}, {15,E4}, {15,E4}, + + /* Line 9. */ + {16,E1}, {16,E1}, {16,E2}, {16,E2}, {17,E1}, {17,E1}, {17,E2}, {17,E2}, + {18,E1}, {18,E1}, {18,E2}, {18,E2}, {19,E1}, {19,E1}, {19,E2}, {19,E2}, + {20,E1}, {20,E1}, {20,E2}, {20,E2}, {21,E1}, {21,E1}, {21,E2}, {21,E2}, + {22,E1}, {22,E1}, {22,E2}, {22,E2}, {23,E1}, {23,E1}, {23,E2}, {23,E2}, + + /* Line 10. */ + {16,E1}, {16,E1}, {16,E2}, {16,E2}, {17,E1}, {17,E1}, {17,E2}, {17,E2}, + {18,E1}, {18,E1}, {18,E2}, {18,E2}, {19,E1}, {19,E1}, {19,E2}, {19,E2}, + {20,E1}, {20,E1}, {20,E2}, {20,E2}, {21,E1}, {21,E1}, {21,E2}, {21,E2}, + {22,E1}, {22,E1}, {22,E2}, {22,E2}, {23,E1}, {23,E1}, {23,E2}, {23,E2}, + + /* Line 11. */ + {16,E3}, {16,E3}, {16,E4}, {16,E4}, {17,E3}, {17,E3}, {17,E4}, {17,E4}, + {18,E3}, {18,E3}, {18,E4}, {18,E4}, {19,E3}, {19,E3}, {19,E4}, {19,E4}, + {20,E3}, {20,E3}, {20,E4}, {20,E4}, {21,E3}, {21,E3}, {21,E4}, {21,E4}, + {22,E3}, {22,E3}, {22,E4}, {22,E4}, {23,E3}, {23,E3}, {23,E4}, {23,E4}, + + /* Line 12. */ + {16,E3}, {16,E3}, {16,E4}, {16,E4}, {17,E3}, {17,E3}, {17,E4}, {17,E4}, + {18,E3}, {18,E3}, {18,E4}, {18,E4}, {19,E3}, {19,E3}, {19,E4}, {19,E4}, + {20,E3}, {20,E3}, {20,E4}, {20,E4}, {21,E3}, {21,E3}, {21,E4}, {21,E4}, + {22,E3}, {22,E3}, {22,E4}, {22,E4}, {23,E3}, {23,E3}, {23,E4}, {23,E4}, + + /* Line 13. */ + {24,E1}, {24,E1}, {24,E2}, {24,E2}, {25,E1}, {25,E1}, {25,E2}, {25,E2}, + {26,E1}, {26,E1}, {26,E2}, {26,E2}, {27,E1}, {27,E1}, {27,E2}, {27,E2}, + {28,E1}, {28,E1}, {28,E2}, {28,E2}, {29,E1}, {29,E1}, {29,E2}, {29,E2}, + {30,E1}, {30,E1}, {30,E2}, {30,E2}, {31,E1}, {31,E1}, {31,E2}, {31,E2}, + + /* Line 14. */ + {24,E1}, {24,E1}, {24,E2}, {24,E2}, {25,E1}, {25,E1}, {25,E2}, {25,E2}, + {26,E1}, {26,E1}, {26,E2}, {26,E2}, {27,E1}, {27,E1}, {27,E2}, {27,E2}, + {28,E1}, {28,E1}, {28,E2}, {28,E2}, {29,E1}, {29,E1}, {29,E2}, {29,E2}, + {30,E1}, {30,E1}, {30,E2}, {30,E2}, {31,E1}, {31,E1}, {31,E2}, {31,E2}, + + /* Line 15. */ + {24,E3}, {24,E3}, {24,E4}, {24,E4}, {25,E3}, {25,E3}, {25,E4}, {25,E4}, + {26,E3}, {26,E3}, {26,E4}, {26,E4}, {27,E3}, {27,E3}, {27,E4}, {27,E4}, + {28,E3}, {28,E3}, {28,E4}, {28,E4}, {29,E3}, {29,E3}, {29,E4}, {29,E4}, + {30,E3}, {30,E3}, {30,E4}, {30,E4}, {31,E3}, {31,E3}, {31,E4}, {31,E4}, + + /* Line 16. */ + {24,E3}, {24,E3}, {24,E4}, {24,E4}, {25,E3}, {25,E3}, {25,E4}, {25,E4}, + {26,E3}, {26,E3}, {26,E4}, {26,E4}, {27,E3}, {27,E3}, {27,E4}, {27,E4}, + {28,E3}, {28,E3}, {28,E4}, {28,E4}, {29,E3}, {29,E3}, {29,E4}, {29,E4}, + {30,E3}, {30,E3}, {30,E4}, {30,E4}, {31,E3}, {31,E3}, {31,E4}, {31,E4}, + + /* Line 17. */ + {32,E1}, {32,E1}, {32,E2}, {32,E2}, {33,E1}, {33,E1}, {33,E2}, {33,E2}, + {34,E1}, {34,E1}, {34,E2}, {34,E2}, {35,E1}, {35,E1}, {35,E2}, {35,E2}, + {36,E1}, {36,E1}, {36,E2}, {36,E2}, {37,E1}, {37,E1}, {37,E2}, {37,E2}, + {38,E1}, {38,E1}, {38,E2}, {38,E2}, {39,E1}, {39,E1}, {39,E2}, {39,E2}, + + /* Line 18. */ + {32,E1}, {32,E1}, {32,E2}, {32,E2}, {33,E1}, {33,E1}, {33,E2}, {33,E2}, + {34,E1}, {34,E1}, {34,E2}, {34,E2}, {35,E1}, {35,E1}, {35,E2}, {35,E2}, + {36,E1}, {36,E1}, {36,E2}, {36,E2}, {37,E1}, {37,E1}, {37,E2}, {37,E2}, + {38,E1}, {38,E1}, {38,E2}, {38,E2}, {39,E1}, {39,E1}, {39,E2}, {39,E2}, + + /* Line 19. */ + {32,E3}, {32,E3}, {32,E4}, {32,E4}, {33,E3}, {33,E3}, {33,E4}, {33,E4}, + {34,E3}, {34,E3}, {34,E4}, {34,E4}, {35,E3}, {35,E3}, {35,E4}, {35,E4}, + {36,E3}, {36,E3}, {36,E4}, {36,E4}, {37,E3}, {37,E3}, {37,E4}, {37,E4}, + {38,E3}, {38,E3}, {38,E4}, {38,E4}, {39,E3}, {39,E3}, {39,E4}, {39,E4}, + + /* Line 20. */ + {32,E3}, {32,E3}, {32,E4}, {32,E4}, {33,E3}, {33,E3}, {33,E4}, {33,E4}, + {34,E3}, {34,E3}, {34,E4}, {34,E4}, {35,E3}, {35,E3}, {35,E4}, {35,E4}, + {36,E3}, {36,E3}, {36,E4}, {36,E4}, {37,E3}, {37,E3}, {37,E4}, {37,E4}, + {38,E3}, {38,E3}, {38,E4}, {38,E4}, {39,E3}, {39,E3}, {39,E4}, {39,E4}, + + /* Line 21. */ + {40,E1}, {40,E1}, {40,E2}, {40,E2}, {41,E1}, {41,E1}, {41,E2}, {41,E2}, + {42,E1}, {42,E1}, {42,E2}, {42,E2}, {43,E1}, {43,E1}, {43,E2}, {43,E2}, + {44,E1}, {44,E1}, {44,E2}, {44,E2}, {45,E1}, {45,E1}, {45,E2}, {45,E2}, + {46,E1}, {46,E1}, {46,E2}, {46,E2}, {47,E1}, {47,E1}, {47,E2}, {47,E2}, + + /* Line 22. */ + {40,E1}, {40,E1}, {40,E2}, {40,E2}, {41,E1}, {41,E1}, {41,E2}, {41,E2}, + {42,E1}, {42,E1}, {42,E2}, {42,E2}, {43,E1}, {43,E1}, {43,E2}, {43,E2}, + {44,E1}, {44,E1}, {44,E2}, {44,E2}, {45,E1}, {45,E1}, {45,E2}, {45,E2}, + {46,E1}, {46,E1}, {46,E2}, {46,E2}, {47,E1}, {47,E1}, {47,E2}, {47,E2}, + + /* Line 23. */ + {40,E3}, {40,E3}, {40,E4}, {40,E4}, {41,E3}, {41,E3}, {41,E4}, {41,E4}, + {42,E3}, {42,E3}, {42,E4}, {42,E4}, {43,E3}, {43,E3}, {43,E4}, {43,E4}, + {44,E3}, {44,E3}, {44,E4}, {44,E4}, {45,E3}, {45,E3}, {45,E4}, {45,E4}, + {46,E3}, {46,E3}, {46,E4}, {46,E4}, {47,E3}, {47,E3}, {47,E4}, {47,E4}, + + /* Line 24. */ + {40,E3}, {40,E3}, {40,E4}, {40,E4}, {41,E3}, {41,E3}, {41,E4}, {41,E4}, + {42,E3}, {42,E3}, {42,E4}, {42,E4}, {43,E3}, {43,E3}, {43,E4}, {43,E4}, + {44,E3}, {44,E3}, {44,E4}, {44,E4}, {45,E3}, {45,E3}, {45,E4}, {45,E4}, + {46,E3}, {46,E3}, {46,E4}, {46,E4}, {47,E3}, {47,E3}, {47,E4}, {47,E4}, + + /* Line 25. */ + {48,E1}, {48,E1}, {48,E2}, {48,E2}, {49,E1}, {49,E1}, {49,E2}, {49,E2}, + {50,E1}, {50,E1}, {50,E2}, {50,E2}, {51,E1}, {51,E1}, {51,E2}, {51,E2}, + {52,E1}, {52,E1}, {52,E2}, {52,E2}, {53,E1}, {53,E1}, {53,E2}, {53,E2}, + {54,E1}, {54,E1}, {54,E2}, {54,E2}, {55,E1}, {55,E1}, {55,E2}, {55,E2}, + + /* Line 26. */ + {48,E1}, {48,E1}, {48,E2}, {48,E2}, {49,E1}, {49,E1}, {49,E2}, {49,E2}, + {50,E1}, {50,E1}, {50,E2}, {50,E2}, {51,E1}, {51,E1}, {51,E2}, {51,E2}, + {52,E1}, {52,E1}, {52,E2}, {52,E2}, {53,E1}, {53,E1}, {53,E2}, {53,E2}, + {54,E1}, {54,E1}, {54,E2}, {54,E2}, {55,E1}, {55,E1}, {55,E2}, {55,E2}, + + /* Line 27. */ + {48,E3}, {48,E3}, {48,E4}, {48,E4}, {49,E3}, {49,E3}, {49,E4}, {49,E4}, + {50,E3}, {50,E3}, {50,E4}, {50,E4}, {51,E3}, {51,E3}, {51,E4}, {51,E4}, + {52,E3}, {52,E3}, {52,E4}, {52,E4}, {53,E3}, {53,E3}, {53,E4}, {53,E4}, + {54,E3}, {54,E3}, {54,E4}, {54,E4}, {55,E3}, {55,E3}, {55,E4}, {55,E4}, + + /* Line 28. */ + {48,E3}, {48,E3}, {48,E4}, {48,E4}, {49,E3}, {49,E3}, {49,E4}, {49,E4}, + {50,E3}, {50,E3}, {50,E4}, {50,E4}, {51,E3}, {51,E3}, {51,E4}, {51,E4}, + {52,E3}, {52,E3}, {52,E4}, {52,E4}, {53,E3}, {53,E3}, {53,E4}, {53,E4}, + {54,E3}, {54,E3}, {54,E4}, {54,E4}, {55,E3}, {55,E3}, {55,E4}, {55,E4}, + + /* Line 29. */ + {56,E1}, {56,E1}, {56,E2}, {56,E2}, {57,E1}, {57,E1}, {57,E2}, {57,E2}, + {58,E1}, {58,E1}, {58,E2}, {58,E2}, {59,E1}, {59,E1}, {59,E2}, {59,E2}, + {60,E1}, {60,E1}, {60,E2}, {60,E2}, {61,E1}, {61,E1}, {61,E2}, {61,E2}, + {62,E1}, {62,E1}, {62,E2}, {62,E2}, {63,E1}, {63,E1}, {63,E2}, {63,E2}, + + /* Line 30. */ + {56,E1}, {56,E1}, {56,E2}, {56,E2}, {57,E1}, {57,E1}, {57,E2}, {57,E2}, + {58,E1}, {58,E1}, {58,E2}, {58,E2}, {59,E1}, {59,E1}, {59,E2}, {59,E2}, + {60,E1}, {60,E1}, {60,E2}, {60,E2}, {61,E1}, {61,E1}, {61,E2}, {61,E2}, + {62,E1}, {62,E1}, {62,E2}, {62,E2}, {63,E1}, {63,E1}, {63,E2}, {63,E2}, + +}; + + + + +#endif diff --git a/src/main.c b/src/main.c new file mode 100644 index 0000000..cd50369 --- /dev/null +++ b/src/main.c @@ -0,0 +1,120 @@ +/*---------------------------------------------------------------------------- + * main.c: Main file for the JB's nes Emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +/* SDL's includes */ +#include + +/* Systems */ +#include + +/*nes includes */ +#include "cpu6502.h" +#include "memory.h" +#include "ppu.h" +#include "apu.h" +#include "paddle.h" +#include "debugger.h" +#include "emulator.h" +#include "main.h" + +#include "debug.h" + +/* long option structure */ +static struct option long_options[] = { + {"help", 0, NULL, 'h'}, + {"input", 1, NULL, 'i'}, + {0, 0, 0, 0} +}; + + +/*************************************************** + * + * Display usage of the program. + * + * + */ +void display_usage(void) +{ + fprintf(stderr, "Usage: nes [options] ...\n\n" + "Options:\n" + "--------\n"); + fprintf(stderr, "\n -h, --help "); + fprintf(stderr, "Display the help message."); + fprintf(stderr, "\n -i, --input "); + fprintf(stderr, "Give the file name of the ROM file."); +} + + +/*************************************************** + * + * Main Function. + * + * + */ +int main (int argc, char **argv) +{ + int result = 0; + int c; + char *romName = NULL; + int debug = 0; + + /* Parse the command line. */ + while ((c = getopt_long (argc, argv, "dhi:", long_options, NULL)) != -1) { + switch (c) { + case 'd': + debug = 1; + break; + case 'h': + display_usage(); + break; + case 'i': + romName = optarg; + break; + } + } + + if (romName == NULL) { + fprintf (stderr, "You need to specify an Rom file.\n"); + return -1; + } + + /* Init the Emulator. */ + result = emulator_init (); + if (result != 0) { + fprintf (stderr, "Impossible to init the Emulator.\n"); + return -1; + } + + /* Load the rom. */ + result = emulator_load (romName); + if (result != 0) { + fprintf (stderr, "Impossible to load the Rom.\n"); + return -1; + } + + /* Init the Debugger. */ + if (debug == 1) { + result = debugger_init (); + if (result != 0) { + fprintf (stderr, "Impossible to init the Emulator.\n"); + return -1; + } + } + + /* Loop on the Commands. */ + result = emulator_loop (debug); + if (result != 0) { + DEBUG0 (("Impossible to Loop on the ROM commands.(%d)\n", result)); + return -1; + } + + return 0; +} diff --git a/src/main.h b/src/main.h new file mode 100644 index 0000000..6beba04 --- /dev/null +++ b/src/main.h @@ -0,0 +1,66 @@ +/*---------------------------------------------------------------------------- + * main.h: Main file for the JB's nes Emulator. + * + *---------------------------------------------------------------------------- + * nes: Nintendo Entertainment System Emulator. + * + * Created by Jean-Baptiste Nadal on 12/02/08. + * Copyright 2008. All rights reserved. + *---------------------------------------------------------------------------- + */ + +#ifndef _MAIN_H +#define _MAIN_H + + +#define FALSE 0 +#define TRUE 1 + +/* Functions defined in the emulator.c file. */ +extern int emulator_init (); +extern int emulator_load (char *romName); +extern int emulator_reset (); +extern int emulator_loop (); + +/* Functions defined in the cpu6502.c file. */ +extern int cpu6502_init (); +extern int cpu6502_execOpCode (nes_cpu6502_t *cpu, uint8_t opcode); +extern void printRegs (nes_cpu6502_t *cpu); + +/* Functions defined in the memory.c file. */ +extern int memory_init (); +extern uint8_t memory_fetch (uint16_t addr); +extern uint16_t memory_Read16 (uint16_t hight, uint16_t low); +extern uint8_t memory_Read (uint16_t addr); +extern void memory_Write (uint16_t addr, uint8_t value); +extern void memory_WriteIndirectIndexed (uint8_t addr, uint8_t value); +extern void DumpMemory (uint16_t StartAddr); + +/* Functions defined in the ppu.c file. */ +extern int ppu_init (); +extern uint8_t memory_Read_PPu (uint16_t addr); +extern void memory_Write_PPu (uint16_t addr, uint8_t value); +extern void bitsetPPUStatus (uint8_t flag, uint8_t val); +extern void PPU_RedrawNesScreen (); +extern void PPU_ShowTiles (int page); +extern void PPU_ClearScreen (); +extern void PPU_DMA_SpriteCopy (uint8_t value); + +/* Functions defined in the apu.c file. */ +extern int apu_init (); + +/* Functions defined in the debugger.c file. */ +extern int debugger_init (); +extern void debugger_stop (); + +/* Functions defined in the paddle.c file. */ +extern int paddle_Init (paddle_t *paddle); +extern int paddle_Read (paddle_t *paddle); +extern void paddle_Write (paddle_t *paddle, uint8_t value); + +/* Global Emulator. */ +extern nes_emulator_t emul; + +#define DEBUG 1 + +#endif diff --git a/tools/corecompare/osx/corecompare.xcodeproj/jbnadal.mode1v3 b/tools/corecompare/osx/corecompare.xcodeproj/jbnadal.mode1v3 new file mode 100644 index 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All rights reserved. + * + * $LastChangedDate: 2008-03-21 01:55:10 +0100 (Ven, 21 mar 2008) $ + * $Author: godzil $ + * $HeadURL: svn+ssh://godzil@trac.godzil.net/svn/projects/Quick6502/trunk/corecpu.c $ + * $Revision: 41 $ + * + */ + +/* Depending on the OS, one of these provide the malloc function */ +#include +#include +#include + +/******************************************************************************* + /!\ WARNING this debug tool slow down a lot the emulator! /!\ + /!\ Use it only if you really need it ! /!\ + *******************************************************************************/ +#define TRACE_INSTRUCTIONS + +#ifdef TRACE_INSTRUCTIONS +#define TRACEi(trace) do { printf ("AT PC: [%.2x - ", cpu->memory_opcode_read(cpu->reg_PC -1)); printf trace ; printf("]\n"); } while(0) +#define TRACEiE(trace) do { printf trace ; printf("\n"); } while(0) +#else +#define TRACEi(trace) { } +//#define TRACEiE(trace) { } +#define TRACEiE(trace) do { printf("$%04x - ", cpu->reg_PC - 1); printf trace ; printf("\n"); } while(0) +#endif + +#define _INTERNAL_QUICK6502_CORECPU_ +#include "corecpu.h" + + +/*** Instructions useful macros ***/ +#define INSTRUCTION(s) static inline void I_##s (quick6502_cpu *cpu) + +#define NZ_FLAG_UPDATE(value) cpu->reg_P = (cpu->reg_P & ~(Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + (value & 0x80) | ((value)?0:Q6502_Z_FLAG) + +#define MEMORY_READ_ZP() cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++)) + +#define MEMORY_READ_IX() cpu->memory_read( (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC ) + cpu->reg_X ) & 0xFF) |\ + (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_X + 1) << 8) ) +#define MEMORY_READ_IY() cpu->memory_read( ( cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC ) ) |\ + (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++) + 1) << 8) ) + cpu->reg_Y ) + +#define MEMORY_READ_ZX() cpu->memory_page0_read( (cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_X) ) +#define MEMORY_READ_ZY() cpu->memory_page0_read( (cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_Y) ) + +#define MEMORY_READ_AB() cpu->memory_read( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) )) + +#define MEMORY_READ_AX() cpu->memory_read( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) ) + cpu->reg_X) +#define MEMORY_READ_AY() cpu->memory_read( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) ) + cpu->reg_Y) + + +#define MEMORY_WRITE_ZP(val) cpu->memory_page0_write(cpu->memory_opcode_read(cpu->reg_PC++), val) + +#define MEMORY_WRITE_IX(val) cpu->memory_write( (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC ) + cpu->reg_X ) & 0xFF) |\ + (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_X + 1) << 8) , val) +#define MEMORY_WRITE_IY(val) cpu->memory_write( ( cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC ) ) |\ + (cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++) + 1) << 8) ) + cpu->reg_Y , val) + +#define MEMORY_WRITE_ZX(val) cpu->memory_page0_write( (cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_X), val) +#define MEMORY_WRITE_ZY(val) cpu->memory_page0_write( (cpu->memory_opcode_read(cpu->reg_PC++) + cpu->reg_Y), val) + +#define MEMORY_WRITE_AB(val) cpu->memory_write( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) ), val) + +#define MEMORY_WRITE_AX(val) cpu->memory_write( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) ) + cpu->reg_X, val) +#define MEMORY_WRITE_AY(val) cpu->memory_write( ((cpu->memory_opcode_read(cpu->reg_PC++) ) |\ + (cpu->memory_opcode_read(cpu->reg_PC++) << 8) ) + cpu->reg_Y, val) + + +#define PUSH_S(value) cpu->memory_stack_write(0x100 | (cpu->reg_S--), value) +#define POP_S() (cpu->memory_stack_read (0x100 | (++cpu->reg_S) )) + +#ifdef NO_DECIMAL + +#define ADC_OPERATION(read) do {\ + unsigned short tmp = 0; unsigned char v = read; \ + tmp = cpu->reg_A + v + (cpu->reg_P & Q6502_C_FLAG); \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG | Q6502_V_FLAG)) | \ + (tmp & 0x80) | ((tmp&0xFF)?0:Q6502_Z_FLAG) | \ + ((tmp & 0xFF00)?Q6502_C_FLAG:0) | \ + ( ( ~(cpu->reg_A^v)&(cpu->reg_A^tmp) )&0x80?Q6502_V_FLAG:0 ); \ + cpu->reg_A = tmp & 0xFF; \ +} while(0) + +#define SBC_OPERATION(read) do {\ + unsigned short tmp = 0; unsigned char v = read; \ + tmp = cpu->reg_A - v - (~cpu->reg_P & Q6502_C_FLAG); \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG | Q6502_V_FLAG)) | \ + (tmp & Q6502_N_FLAG) | ((tmp&0xFF)?0:Q6502_Z_FLAG) | \ + ((tmp & 0xFF00)?0:Q6502_C_FLAG) | \ + ( ( (cpu->reg_A^v)&(cpu->reg_A^tmp) )&0x80?Q6502_V_FLAG:0 ); \ + cpu->reg_A = tmp & 0xFF; \ +} while(0) + +#else +#error Quick6502 doesn't actually support DECIMAL mode +#endif + + +#define AND_OPERATION(read) cpu->reg_A &= read; NZ_FLAG_UPDATE(cpu->reg_A) + +/* CMP is like SBC but without storing the result value */ +#define CMP_OPERATION(register, read) do { \ + unsigned short tmp = 0; \ + tmp = register - read; \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + (tmp & Q6502_N_FLAG) | ((tmp&0xFF)?0:Q6502_Z_FLAG) | \ + ((tmp & 0xFF00)?0:Q6502_C_FLAG); \ +} while(0) + +#define EOR_OPERATION(read) cpu->reg_A ^= read; NZ_FLAG_UPDATE(cpu->reg_A) +#define ORA_OPERATION(read) cpu->reg_A |= read; NZ_FLAG_UPDATE(cpu->reg_A) + +#define BIT_OPERATION(read) do { \ + byte tmp = read; \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_V_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + (tmp & Q6502_N_FLAG) | (tmp & Q6502_V_FLAG) | \ + ((tmp & cpu->reg_A)?0:Q6502_Z_FLAG); \ +} while(0) + +#define ASL_OPERATION(val) cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + ((val&0x40)?Q6502_N_FLAG:0) | \ + ((val&0x80)?Q6502_C_FLAG:0) | \ + ((val&0x7F)?0:Q6502_Z_FLAG); \ + val = val << 1 + +#define LSR_OPERATION(val) cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + (val & Q6502_C_FLAG) | \ + ((val&0xFE)?0:Q6502_Z_FLAG); \ + val = val >> 1 + +#define ROR_OPERATION(val) do {\ + unsigned short tmp = val | (cpu->reg_P & Q6502_C_FLAG) << 8; \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + ( tmp&Q6502_C_FLAG) | /* Set the C flag */ \ + ((tmp&0x100) >> 1) | /* Set the N flag */ \ + ((tmp&0x1FE)?0:Q6502_Z_FLAG); /* 0x1FE will be the new 8bit value */ \ + val = (tmp>>1) & 0xFF; \ +} while(0) + +#define ROL_OPERATION(val) do {\ +unsigned short tmp = (val << 1) | (cpu->reg_P & Q6502_C_FLAG); \ + cpu->reg_P = (cpu->reg_P & ~(Q6502_C_FLAG | Q6502_N_FLAG | Q6502_Z_FLAG)) | \ + ((tmp&0x100)?Q6502_C_FLAG:0) | /* Set the C flag */ \ + ((tmp&0x80)) | /* Set the N flag */ \ + ((tmp&0xFF)?0:Q6502_Z_FLAG); /* 0x1FE will be the new 8bit value */ \ + val = tmp & 0xFF; \ +} while(0) + + +/** Function used for execution of instruction */ +static inline int quick6502_exec_one(quick6502_cpu *cpu); + +/** + * Initialise the CPU + * + * Inputs: + * + * - CPU Init structure: + * - Memory Read function pointer + * - Memory Write function pointer + * - Fast memory read function pointer (for opcodes read) + * - Fast page 0 function Read/Write + * - Fast page 1 function Read/Write + * + * Output: + * + * (void *): An opaque pointer to the internal structure of the CPU. + * NULL if an error occured ! + */ +quick6502_cpu *quick6502_init(quick6502_cpuconfig *config) +{ + quick6502_cpu *cpu; + + /* Alloc structure */ + cpu = (quick6502_cpu *) malloc (sizeof (quick6502_cpu)); + if (!cpu) + return NULL; + + /* Initialise other variables */ + cpu->running = 0; /* CPU is currently NOT running */ + + cpu->cycle_done = 0; + + /* Initialise registers */ + cpu->reg_A = 0; + cpu->reg_X = 0; + cpu->reg_Y = 0; + cpu->reg_S = 0xFF; + + cpu->reg_P = Q6502_D_FLAG | Q6502_I_FLAG; + + if (config->memory_read != NULL) + cpu->memory_read = config->memory_read; + else + goto init_error; + + if (config->memory_write != NULL) + cpu->memory_write = config->memory_write; + else + goto init_error; + + if (config->memory_opcode_read != NULL) + cpu->memory_opcode_read = config->memory_opcode_read; + else + cpu->memory_opcode_read = config->memory_read; + + + if (config->memory_page0_read != NULL) + cpu->memory_page0_read = config->memory_page0_read; + else + cpu->memory_page0_read = config->memory_read; + + if (config->memory_page0_write != NULL) + cpu->memory_page0_write = config->memory_page0_write; + else + cpu->memory_page0_write = config->memory_write; + + if (config->memory_stack_read != NULL) + cpu->memory_stack_read = config->memory_stack_read; + else + cpu->memory_stack_read = config->memory_read; + + if (config->memory_stack_write != NULL) + cpu->memory_stack_write = config->memory_stack_write; + else + cpu->memory_stack_write = config->memory_write; + + return cpu; + +init_error: + if (cpu) + free (cpu); + + return NULL; +} + + +/** Reset the CPU (must be done after init) */ +void quick6502_reset(quick6502_cpu *cpu) +{ + /* Initialise registers */ + /*cpu->reg_A = 0; + cpu->reg_X = 0; + cpu->reg_Y = 0; + cpu->reg_S = 0xFF;*/ + + //cpu->reg_P = Q6502_D_FLAG | Q6502_I_FLAG | 0x20 | Q6502_B_FLAG; + + /* Set the PC to the RESET vector */ + cpu->reg_PC = ( cpu->memory_read(Q6502_RESET_HIGH) << 8) + | cpu->memory_read(Q6502_RESET_LOW); + + cpu->exit_loop = 0; +} + +/** + * Run cpu for at least X cycles + * + * Output: + * + * int: (Number of cycle really done) - (Number of cycle asked) + */ +int quick6502_run(quick6502_cpu *cpu, int cycles) +{ + cpu->running = !0; + + while(cpu->cycle_done < cycles) + { + quick6502_exec_one(cpu); + } + cpu->cycle_done -= cycles; + + cpu->running = 0; + + return cycles + cpu->cycle_done; +} + +/** Loop CPU until explicit quit */ +void quick6502_loop(quick6502_cpu *cpu) +{ + cpu->running = !0; + while(cpu->exit_loop) + { + quick6502_exec_one(cpu); + } + cpu->running = 0; +} + +/** Run CPU for one instruction */ +void quick6502_exec(quick6502_cpu *cpu) +{ + cpu->running = !0; + quick6502_exec_one(cpu); + cpu->running = 0; +} + +/** Send IRQ/NMI/EXITLOOP signal to CPU */ +void quick6502_int(quick6502_cpu *cpu, quick6502_signal signal) +{ + switch(signal) + { + default: + break; + + case Q6502_IRQ_SIGNAL: + if (! (cpu->reg_P & Q6502_I_FLAG) ) + { + TRACEi(("IRQ Triggered !")); + PUSH_S((cpu->reg_PC >> 8) & 0xFF ); + PUSH_S((cpu->reg_PC ) & 0xFF ); + PUSH_S( cpu->reg_P & ~Q6502_B_FLAG ); + cpu->reg_P = cpu->reg_P | Q6502_I_FLAG; + + cpu->reg_PC = (cpu->memory_read(Q6502_IRQ_LOW)) | (cpu->memory_read(Q6502_IRQ_HIGH)<<8); + + cpu->cycle_done += 7; + } + break; + + case Q6502_NMI_SIGNAL: + TRACEi(("NMI Triggered !")); + PUSH_S((cpu->reg_PC >> 8) & 0xFF ); + PUSH_S((cpu->reg_PC ) & 0xFF ); + PUSH_S( cpu->reg_P ); + cpu->reg_P = cpu->reg_P | Q6502_I_FLAG; + + cpu->reg_PC = (cpu->memory_read(Q6502_NMI_LOW)) | (cpu->memory_read(Q6502_NMI_HIGH)<<8); + + cpu->cycle_done += 7; + break; + + case Q6502_STOPLOOP_SIGNAL: + cpu->exit_loop = 1; + break; + } +} + +/** Dump CPU State to the given file */ +void quick6502_dump(quick6502_cpu *cpu, FILE * fp) +{ + short i; + char instr[20]; + /* Display registers */ + fprintf(fp, + "Quick6502: PC:$%04x A:$%02x X:$%02x Y:$%02x S:$%02x P:$%02x P:[%c%c%c%c%c%c%c%c] Stack[%2.2x, %2.2x, %2.2x]\n", + cpu->reg_PC, cpu->reg_A, cpu->reg_X, cpu->reg_Y, cpu->reg_S, cpu->reg_P, + cpu->reg_P&Q6502_N_FLAG ? 'N':'.', + cpu->reg_P&Q6502_V_FLAG ? 'V':'.', + '.', /* No real flag here */ + cpu->reg_P&Q6502_B_FLAG ? 'B':'.', + cpu->reg_P&Q6502_D_FLAG ? 'D':'.', + cpu->reg_P&Q6502_I_FLAG ? 'I':'.', + cpu->reg_P&Q6502_Z_FLAG ? 'Z':'.', + cpu->reg_P&Q6502_C_FLAG ? 'C':'.', + cpu->memory_stack_read (0x100 | (cpu->reg_S+1)), + cpu->memory_stack_read (0x100 | (cpu->reg_S+2)), + cpu->memory_stack_read (0x100 | (cpu->reg_S+3))); + + /* Display stack */ + fprintf(fp, "Quick6502: Stack: [ "); + for (i = cpu->reg_S+1; i < 0x100; i++) + { + fprintf(fp, "$%02x ", cpu->memory_opcode_read(0x100 | i)); + } + fprintf(fp, "] Run:%c Cycle:%ld\n", cpu->running?'Y':'N', cpu->cycle_done); + + quick6502_getinstruction(cpu, cpu->reg_PC, instr); + fprintf(fp, "Quick6502: Instruction at PC: %s\n", instr); +} + +/** Get current instruction name at specified address and put it into buffer */ +void quick6502_getinstruction(quick6502_cpu *cpu, unsigned short addr, char *buffer) +{ + buffer[0] = 0; +} + +/** + * Free the CPU + * + * This function will free the CPU only if it's not currently used, it will + * return !0 if everything goes well and 0 if the free is impossible + */ +int quick6502_free(quick6502_cpu *cpu) +{ + + return 0; +} + +/******************************************************************************* + *** Here start real CPU logic *** + *******************************************************************************/ +static byte CycleTable[256] = +{ +/* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F */ +/* 00 */ 7, 6, 2, 1, 5, 3, 5, 5, 3, 2, 2, 1, 6, 4, 6, 2, +/* 10 */ 2, 5, 5, 1, 5, 4, 6, 5, 2, 4, 2, 1, 6, 4, 6, 2, +/* 20 */ 6, 6, 2, 1, 3, 3, 5, 5, 4, 2, 2, 1, 4, 4, 6, 2, +/* 30 */ 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 2, 1, 4, 4, 6, 2, +/* 40 */ 6, 6, 2, 1, 3, 3, 5, 5, 3, 2, 2, 1, 3, 4, 6, 2, +/* 50 */ 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 3, 1, 8, 4, 6, 2, +/* 60 */ 6, 6, 2, 1, 3, 3, 5, 5, 4, 2, 2, 1, 6, 4, 6, 2, +/* 70 */ 2, 5, 5, 1, 4, 4, 6, 5, 5, 4, 4, 1, 6, 4, 6, 2, +/* 80 */ 3, 6, 2, 1, 3, 3, 3, 5, 2, 2, 2, 1, 4, 4, 4, 2, +/* 90 */ 2, 6, 5, 1, 4, 4, 4, 5, 2, 5, 2, 1, 4, 5, 5, 2, +/* A0 */ 2, 6, 2, 1, 3, 3, 3, 5, 2, 2, 2, 1, 4, 4, 4, 2, +/* B0 */ 2, 5, 5, 1, 4, 4, 4, 5, 2, 4, 2, 1, 4, 4, 4, 2, +/* C0 */ 2, 6, 2, 1, 3, 3, 5, 5, 2, 2, 2, 2, 4, 4, 6, 2, +/* D0 */ 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 3, 2, 4, 4, 6, 2, +/* E0 */ 2, 6, 2, 1, 3, 3, 5, 5, 2, 2, 2, 1, 4, 4, 6, 2, +/* F0 */ 2, 5, 5, 1, 4, 4, 6, 5, 2, 4, 4, 1, 4, 4, 6, 2 +/* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F */ +}; + +typedef void (*InstructionFunction)(quick6502_cpu *cpu); + +/******************************************************************************* + * Instruction implementations + *******************************************************************************/ + +/**** Other instructions ****/ +INSTRUCTION(ILLEG) +{ + TRACEiE(("Illegal instruction $%02x", cpu->memory_opcode_read(cpu->reg_PC-1))); + //exit(-1); +} + +/** 58 : CLI - CLear Interrupt **/ +INSTRUCTION(CLIiM) +{ + TRACEi(("CLC")); + cpu->reg_P &= ~Q6502_I_FLAG; +} +/** 78 : SEI - SEt Interrupt **/ +INSTRUCTION(SEIiM) +{ + TRACEi(("SEI")); + cpu->reg_P |= Q6502_I_FLAG; +} + +/** 18 : CLC - CLear Carry **/ +INSTRUCTION(CLCiM) +{ + TRACEi(("CLC")); + cpu->reg_P &= ~Q6502_C_FLAG; +} +/** 38 : SEC - SEt Carry **/ +INSTRUCTION(SECiM) +{ + TRACEi(("SEC")); + cpu->reg_P |= Q6502_C_FLAG; +} + +/** D8 : CLD - CLear Decimal **/ +INSTRUCTION(CLDiM) +{ + TRACEi(("CLD")); + cpu->reg_P &= ~Q6502_D_FLAG; +} +/** F8 : SED - SEt Decimal **/ +INSTRUCTION(SEDiM) +{ + TRACEi(("SED")); + cpu->reg_P |= Q6502_D_FLAG; +} +/** B8 : CLV - CLear oVerflo **/ +INSTRUCTION(CLViM) +{ + TRACEi(("CLV")); + cpu->reg_P &= ~Q6502_V_FLAG; +} + +/** EA : NOP - NO oPeration **/ +INSTRUCTION(NOPiM) +{ + TRACEi(("NOP")); +} + +/**** Load/Store functions ****/ + +/** A9 : LDA #$xx - LoaD an immediate value into A */ +INSTRUCTION(LDAiM) +{ + TRACEi(("LDA #$%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = cpu->memory_opcode_read(cpu->reg_PC++); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** A2 : LDX #$xx - LoaD an immediate value into X */ +INSTRUCTION(LDXiM) +{ + TRACEi(("LDX #$%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_X = cpu->memory_opcode_read(cpu->reg_PC++); + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** A0 : LDY #$xx - LoaD an immediate value into Y */ +INSTRUCTION(LDYiM) +{ + TRACEi(("LDY #$%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_Y = cpu->memory_opcode_read(cpu->reg_PC++); + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** A5: LDA $xx - LoaD to A from zero page **/ +INSTRUCTION(LDAzP) +{ + TRACEi(("LDA $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_ZP(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** B5: LDA $xx,X - LoaD to A **/ +INSTRUCTION(LDAzX) +{ + TRACEi(("LDA $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_ZX(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** A1: LDA ($xx,X) - LoaD to A **/ +INSTRUCTION(LDAiX) +{ + TRACEi(("LDA ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_IX(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** B1: LDA ($xx),Y - LoaD to A **/ +INSTRUCTION(LDAiY) +{ + TRACEi(("LDA ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_IY(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** AD: LDA $xxxx - LoaD to A **/ +INSTRUCTION(LDAaB) +{ + TRACEi(("LDA $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_AB(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** DD: LDA $xxxx,X - LoaD to A **/ +INSTRUCTION(LDAaX) +{ + TRACEi(("LDA $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_AX(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** D9: LDA $xxxx,Y - LoaD to A **/ +INSTRUCTION(LDAaY) +{ + TRACEi(("LDA $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_A = MEMORY_READ_AY(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** 85: STA $xx - STore A to zero page **/ +INSTRUCTION(STAzP) +{ + TRACEi(("STA $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->memory_page0_write(cpu->memory_opcode_read(cpu->reg_PC++), cpu->reg_A); +} + +/** 95: STA $xx,X - STore A **/ +INSTRUCTION(STAzX) +{ + TRACEi(("STA $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_ZX(cpu->reg_A); +} + +/** 81: STA ($xx,X) - STore A **/ +INSTRUCTION(STAiX) +{ + TRACEi(("STA ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_IX(cpu->reg_A); +} + +/** 91: STA ($xx),Y - STore A **/ +INSTRUCTION(STAiY) +{ + TRACEi(("STA ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_IY(cpu->reg_A); +} + +/** 8D: STA $xxxx - STore A **/ +INSTRUCTION(STAaB) +{ + TRACEi(("STA $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_AB(cpu->reg_A); +} + +/** 9D: STA $xxxx,X - STore A **/ +INSTRUCTION(STAaX) +{ + TRACEi(("STA $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_AX(cpu->reg_A); +} + +/** 99: STA $xxxx,Y - STore A **/ +INSTRUCTION(STAaY) +{ + TRACEi(("STA $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_AY(cpu->reg_A); +} + +/** A6: LDX $xx - LoaD to X from zero page **/ +INSTRUCTION(LDXzP) +{ + TRACEi(("LDX $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_X = MEMORY_READ_ZP(); + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** B6: LDX $xx,Y - LoaD to X **/ +INSTRUCTION(LDXzY) +{ + TRACEi(("LDX $%02x,Y", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_X = MEMORY_READ_ZY(); + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** AE: LDX $xxxx - LoaD to X **/ +INSTRUCTION(LDXaB) +{ + TRACEi(("LDX $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_X = MEMORY_READ_AB(); + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** BE: LDX $xxxx,Y - LoaD to X **/ +INSTRUCTION(LDXaY) +{ + TRACEi(("LDX $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_X = MEMORY_READ_AY(); + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** B6: STX $xx - STore X to zero page **/ +INSTRUCTION(STXzP) +{ + TRACEi(("STX $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->memory_page0_write(cpu->memory_opcode_read(cpu->reg_PC++), cpu->reg_X); +} + +/** 96: STX $xx,Y - STore X **/ +INSTRUCTION(STXzY) +{ + TRACEi(("STX $%02x,Y", cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_ZY(cpu->reg_X); +} + +/** 8E: STX $xxxx - STore X **/ +INSTRUCTION(STXaB) +{ + TRACEi(("STX $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_AB(cpu->reg_X); +} + +/** A4: LDY $xx - LoaD to Y from zero page **/ +INSTRUCTION(LDYzP) +{ + TRACEi(("LDY $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_Y = MEMORY_READ_ZP(); + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** B4: LDY $xx,X - LoaD to Y **/ +INSTRUCTION(LDYzX) +{ + TRACEi(("LDY $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_Y = MEMORY_READ_ZX(); + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** AC: LDY $xxxx - LoaD to Y **/ +INSTRUCTION(LDYaB) +{ + TRACEi(("LDY $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_Y = MEMORY_READ_AB(); + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** BC: LDY $xxxx,X - LoaD to Y **/ +INSTRUCTION(LDYaX) +{ + TRACEi(("LDY $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_Y = MEMORY_READ_AX(); + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** 84: STY $xx - STore Y to zero page **/ +INSTRUCTION(STYzP) +{ + TRACEi(("STY $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + cpu->memory_page0_write(cpu->memory_opcode_read(cpu->reg_PC++), cpu->reg_Y); +} + +/** 94: STY $xx,X - STore Y **/ +INSTRUCTION(STYzX) +{ + TRACEi(("STY $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_ZX(cpu->reg_Y); +} + +/** 8C: STY $xxxx - STore Y **/ +INSTRUCTION(STYaB) +{ + TRACEi(("STY $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + MEMORY_WRITE_AB(cpu->reg_Y); +} + +/**** Register functions ****/ + +/** AA : TAX - Transfer A to X **/ +INSTRUCTION(TAXiM) +{ + TRACEi(("TAX")); + cpu->reg_X = cpu->reg_A; + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** 8A : TXA - Transfer X to A **/ +INSTRUCTION(TXAiM) +{ + TRACEi(("TXA")); + cpu->reg_A = cpu->reg_X; + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** A8 : TAY - Transfer A to Y **/ +INSTRUCTION(TAYiM) +{ + TRACEi(("TAY")); + cpu->reg_Y = cpu->reg_A; + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** 98 : TYA - Transfer Y to A **/ +INSTRUCTION(TYAiM) +{ + TRACEi(("TYA")); + cpu->reg_A = cpu->reg_Y; + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/* BA : TSX - Transfer S to X **/ +INSTRUCTION(TSXiM) +{ + TRACEi(("TSX")); + cpu->reg_X = cpu->reg_S; + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** 9A : TXS - Transfer X to S **/ +INSTRUCTION(TXSiM) +{ + TRACEi(("TXS")); + cpu->reg_S = cpu->reg_X; +} + +/**** Simple register operation instructions ****/ + +/** CA : DEX - DEcrement X **/ +INSTRUCTION(DEXiM) +{ + TRACEi(("DEX")); + cpu->reg_X --; + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** 88 : DEY - DEcrement Y **/ +INSTRUCTION(DEYiM) +{ + TRACEi(("DEY")); + cpu->reg_Y --; + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/** E8 : INX - INcrement X **/ +INSTRUCTION(INXiM) +{ + TRACEi(("INX")); + cpu->reg_X ++; + NZ_FLAG_UPDATE(cpu->reg_X); +} + +/** C8 : INY - INcrement Y **/ +INSTRUCTION(INYiM) +{ + TRACEi(("INY")); + cpu->reg_Y ++; + NZ_FLAG_UPDATE(cpu->reg_Y); +} + +/**** Stack related instructions ****/ + +/** 48 : PHA - PusH A */ +INSTRUCTION(PHAiM) +{ + TRACEi(("PHA")); + PUSH_S(cpu->reg_A); +} + +/** 68 : PLA - PuLl A */ +INSTRUCTION(PLAiM) +{ + TRACEi(("PLA")); + cpu->reg_A = POP_S(); + NZ_FLAG_UPDATE(cpu->reg_A); +} + +/** 08 : PHP - PusH P */ +INSTRUCTION(PHPiM) +{ + TRACEi(("PHP")); + PUSH_S((cpu->reg_P | Q6502_R_FLAG | Q6502_B_FLAG)); +} + +/** 28 : PLP - PuLl P */ +INSTRUCTION(PLPiM) +{ + TRACEi(("PLP")); + cpu->reg_P = POP_S() & ~(Q6502_R_FLAG | Q6502_B_FLAG); +} + +/**** Branch instructions ****/ + +/** 20 : JSR $xxxx - Jump to SubRoutine */ +INSTRUCTION(JSRaB) +{ + TRACEi(("JSR $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_PC++; + PUSH_S((cpu->reg_PC >> 8) & 0xFF); + PUSH_S((cpu->reg_PC ) & 0xFF); + cpu->reg_PC = ((cpu->memory_opcode_read(cpu->reg_PC-1) ) | (cpu->memory_opcode_read(cpu->reg_PC) << 8)); +} + +/** 60 : RTS - ReTurn from Subrutine */ +INSTRUCTION(RTSiM) +{ + TRACEi(("RTS")); + cpu->reg_PC = POP_S() | (POP_S() << 8); + cpu->reg_PC ++; +} + +/** 4C : JMP $xxxx - JuMP inconditionaly to $xxxx **/ +INSTRUCTION(JMPaB) +{ + TRACEi(("JMP $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_PC = ((cpu->memory_opcode_read(cpu->reg_PC++ ) ) | (cpu->memory_opcode_read(cpu->reg_PC) << 8)); +} + +/** 6C : JMP ($xxxx) - JuMP inconditionaly to ($xxxx) **/ +INSTRUCTION(JMPiD) +{ + TRACEi(("JMP ($%02x%02x)", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + cpu->reg_PC = (cpu->memory_opcode_read(cpu->reg_PC++)) | (cpu->memory_opcode_read(cpu->reg_PC++)<<8); + cpu->reg_PC = (cpu->memory_read(cpu->reg_PC++)) | (cpu->memory_read(cpu->reg_PC++)<<8); +} + +/** 00 : BRK - BReaK **/ +INSTRUCTION(BRKiM) +{ + TRACEi(("BRK")); + PUSH_S((cpu->reg_PC >> 8) & 0xFF); + PUSH_S((cpu->reg_PC ) & 0xFF); + PUSH_S( cpu->reg_P ); + cpu->reg_P = cpu->reg_P | Q6502_I_FLAG | Q6502_B_FLAG; + + cpu->reg_PC = (cpu->memory_read(Q6502_IRQ_LOW)) | (cpu->memory_read(Q6502_IRQ_HIGH)<<8); +} + +/** 40 : RTI - ReTurn from Interruption **/ +INSTRUCTION(RTIiM) +{ + TRACEi(("RTI")); + cpu->reg_P = POP_S(); + cpu->reg_PC = POP_S() | (POP_S() << 8); +} + +/** 90 : BCC - Branch if Carry Clear **/ +INSTRUCTION(BCCrE) +{ + TRACEi(("BCC $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (!(cpu->reg_P & Q6502_C_FLAG)) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** B0 : BCS - Branch if Carry Set**/ +INSTRUCTION(BCSrE) +{ + TRACEi(("BCS $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (cpu->reg_P & Q6502_C_FLAG) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** F0 : BEQ - Branch if Equal**/ +INSTRUCTION(BEQrE) +{ + TRACEi(("BEQ $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (cpu->reg_P & Q6502_Z_FLAG) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** 30 : BMI - Branch if MInus**/ +INSTRUCTION(BMIrE) +{ + TRACEi(("BMI $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (cpu->reg_P & Q6502_N_FLAG) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** D0 : Bxx - Branch if Not Equal**/ +INSTRUCTION(BNErE) +{ + TRACEi(("BNE $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (!(cpu->reg_P & Q6502_Z_FLAG)) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** 10 : BPL - Branch if PLus **/ +INSTRUCTION(BPLrE) +{ + TRACEi(("BPL $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (!(cpu->reg_P & Q6502_N_FLAG)) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** 50 : BVC - Branch if oVerflow Clear**/ +INSTRUCTION(BVCrE) +{ + TRACEi(("BVC $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (!(cpu->reg_P & Q6502_V_FLAG)) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/** 70 : BVS - Branch if oVerflow Set**/ +INSTRUCTION(BVSrE) +{ + TRACEi(("BVS $%04x", cpu->reg_PC + (signed char) cpu->memory_opcode_read(cpu->reg_PC) + 1)); + if (cpu->reg_P & Q6502_V_FLAG) + { + cpu->reg_PC += (signed char) cpu->memory_opcode_read(cpu->reg_PC ++) + 1; + /* Need to set timing */ + + /* +1 is same page */ + + /* +2 is another */ + } + else + cpu->reg_PC ++; +} + +/*** Mathematical functions ***/ + +/** 69 : ADC - ADd with Carry **/ +INSTRUCTION(ADCiM) +{ + TRACEi(("ADC #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + ADC_OPERATION(cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** 65 : ADC - ADd with Carry **/ +INSTRUCTION(ADCzP) +{ + TRACEi(("ADC $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + ADC_OPERATION(MEMORY_READ_ZP()); +} + +/** 75 : ADC - ADd with Carry **/ +INSTRUCTION(ADCzX) +{ + TRACEi(("ADC $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + ADC_OPERATION(MEMORY_READ_ZX()); +} + +/** 61 : ADC - ADd with Carry **/ +INSTRUCTION(ADCiX) +{ + TRACEi(("ADC ($%02,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + ADC_OPERATION(MEMORY_READ_IX()); +} + +/** 71 : ADC - ADd with Carry **/ +INSTRUCTION(ADCiY) +{ + TRACEi(("ADC ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + ADC_OPERATION(MEMORY_READ_IY()); +} + +/** 6D : ADC - ADd with Carry **/ +INSTRUCTION(ADCaB) +{ + TRACEi(("ADC $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ADC_OPERATION(MEMORY_READ_AB()); +} + +/** 7D : ADC - ADd with Carry **/ +INSTRUCTION(ADCaX) +{ + TRACEi(("ADC $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ADC_OPERATION(MEMORY_READ_AX()); +} + +/** 79 : ADC - ADd with Carry **/ +INSTRUCTION(ADCaY) +{ + TRACEi(("ADC $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ADC_OPERATION(MEMORY_READ_AY()); +} + +/** E9 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCiM) +{ + TRACEi(("SBC #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + SBC_OPERATION(cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** E5 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCzP) +{ + TRACEi(("SBC $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + SBC_OPERATION(MEMORY_READ_ZP()); +} + +/** F5 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCzX) +{ + TRACEi(("SBC $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + SBC_OPERATION(MEMORY_READ_ZX()); +} + +/** E1 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCiX) +{ + TRACEi(("SBC ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + SBC_OPERATION(MEMORY_READ_IX()); +} + +/** F1 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCiY) +{ + TRACEi(("SBC ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + SBC_OPERATION(MEMORY_READ_IY()); +} + +/** ED : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCaB) +{ + TRACEi(("SBC $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + SBC_OPERATION(MEMORY_READ_AB()); +} + +/** FD : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCaX) +{ + TRACEi(("SBC $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + SBC_OPERATION(MEMORY_READ_AX()); +} + +/** F9 : SBC - SuBstract with Carry **/ +INSTRUCTION(SBCaY) +{ + TRACEi(("SBC $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + SBC_OPERATION(MEMORY_READ_AY()); +} + +/** C9 : CMP - CoMPare **/ +INSTRUCTION(CMPiM) +{ + TRACEi(("CMP #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + CMP_OPERATION(cpu->reg_A, cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** C5 : CMP - CoMPare **/ +INSTRUCTION(CMPzP) +{ + TRACEi(("CMP $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_ZP()); +} + +/** D5 : CMP - CoMPare **/ +INSTRUCTION(CMPzX) +{ + TRACEi(("CMP $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_ZX()); +} + +/** C1 : CMP - CoMPare **/ +INSTRUCTION(CMPiX) +{ + TRACEi(("CMP ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_IX()); +} + +/** D1 : CMP - CoMPare **/ +INSTRUCTION(CMPiY) +{ + TRACEi(("CMP ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_IY()); +} + +/** CD : CMP - CoMPare **/ +INSTRUCTION(CMPaB) +{ + TRACEi(("CMP $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_AB()); +} + +/** DD : CMP - CoMPare **/ +INSTRUCTION(CMPaX) +{ + TRACEi(("CMP $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_AX()); +} + +/** D9 : CMP - CoMPare **/ +INSTRUCTION(CMPaY) +{ + TRACEi(("CMP $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_A, MEMORY_READ_AY()); +} + +/** E0 : CPX - ComPare with Y **/ +INSTRUCTION(CPXiM) +{ + TRACEi(("CPX #$%02x", cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_X, cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** E4 : CPX - ComPare with X **/ +INSTRUCTION(CPXzP) +{ + TRACEi(("CPX $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_X, MEMORY_READ_ZP()); +} + +/** EC : CPX - ComPare with X **/ +INSTRUCTION(CPXaB) +{ + TRACEi(("CPX $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_X, MEMORY_READ_AB()); +} + +/** C0 : CPY - ComPare with Y **/ +INSTRUCTION(CPYiM) +{ + TRACEi(("CPY #$%02x", cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_Y, cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** C4 : CPY - ComPare with Y **/ +INSTRUCTION(CPYzP) +{ + TRACEi(("CPY $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_Y, MEMORY_READ_ZP()); +} + +/** CC : CPY - ComPare with Y **/ +INSTRUCTION(CPYaB) +{ + TRACEi(("CPY $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + CMP_OPERATION(cpu->reg_Y, MEMORY_READ_AB()); +} + +/** 09 : ORA - OR with A **/ +INSTRUCTION(ORAiM) +{ + TRACEi(("ORA #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + ORA_OPERATION(cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** 405 : ORA - OR with A **/ +INSTRUCTION(ORAzP) +{ + TRACEi(("ORA $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + ORA_OPERATION(cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++))); +} + +/** 15 : ORA - OR with A **/ +INSTRUCTION(ORAzX) +{ + TRACEi(("ORA $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + ORA_OPERATION(MEMORY_READ_ZX()); +} + +/** 01 : ORA - OR with A **/ +INSTRUCTION(ORAiX) +{ + TRACEi(("ORA ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + ORA_OPERATION(MEMORY_READ_IX()); +} + +/** 11 : ORA - OR with A **/ +INSTRUCTION(ORAiY) +{ + TRACEi(("ORA ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + ORA_OPERATION(MEMORY_READ_IY()); +} + +/** 0D : ORA - OR with A **/ +INSTRUCTION(ORAaB) +{ + TRACEi(("ORA $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ORA_OPERATION(MEMORY_READ_AB()); +} + +/** 1D : ORA - OR with A **/ +INSTRUCTION(ORAaX) +{ + TRACEi(("ORA $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ORA_OPERATION(MEMORY_READ_AX()); +} + +/** 19 : ORA - OR with A **/ +INSTRUCTION(ORAaY) +{ + TRACEi(("ORA $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + ORA_OPERATION(MEMORY_READ_AY()); +} + +/** 49 : EOR - Exclusive OR **/ +INSTRUCTION(EORiM) +{ + TRACEi(("EOR #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + EOR_OPERATION(cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** 45 : EOR - Exclusive OR **/ +INSTRUCTION(EORzP) +{ + TRACEi(("EOR $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + EOR_OPERATION(cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++))); +} + +/** 55 : EOR - Exclusive OR **/ +INSTRUCTION(EORzX) +{ + TRACEi(("EOR $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + EOR_OPERATION(MEMORY_READ_ZX()); +} + +/** 41 : EOR - Exclusive OR **/ +INSTRUCTION(EORiX) +{ + TRACEi(("EOR ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + EOR_OPERATION(MEMORY_READ_IX()); +} + +/** 51 : EOR - Exclusive OR **/ +INSTRUCTION(EORiY) +{ + TRACEi(("EOR ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + EOR_OPERATION(MEMORY_READ_IY()); +} + +/** 4D : EOR - Exclusive OR **/ +INSTRUCTION(EORaB) +{ + TRACEi(("EOR $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + EOR_OPERATION(MEMORY_READ_AB()); +} + +/** 5D : EOR - Exclusive OR **/ +INSTRUCTION(EORaX) +{ + TRACEi(("EOR $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + EOR_OPERATION(MEMORY_READ_AX()); +} + +/** 59 : EOR - Exclusive OR **/ +INSTRUCTION(EORaY) +{ + TRACEi(("EOR $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + EOR_OPERATION(MEMORY_READ_AY()); +} + +/** 29 : AND - Logical AND **/ +INSTRUCTION(ANDiM) +{ + TRACEi(("AND #$%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + AND_OPERATION(cpu->memory_opcode_read(cpu->reg_PC++)); +} + +/** 25 : AND - Logical AND **/ +INSTRUCTION(ANDzP) +{ + TRACEi(("AND $%02x", cpu->memory_opcode_read(cpu->reg_PC) )); + AND_OPERATION(cpu->memory_page0_read(cpu->memory_opcode_read(cpu->reg_PC++))); +} + +/** 35 : AND - Logical AND **/ +INSTRUCTION(ANDzX) +{ + TRACEi(("AND $%02x,X", cpu->memory_opcode_read(cpu->reg_PC) )); + AND_OPERATION(MEMORY_READ_ZX()); +} + +/** 21 : AND - Logical AND **/ +INSTRUCTION(ANDiX) +{ + TRACEi(("AND ($%02x,X)", cpu->memory_opcode_read(cpu->reg_PC) )); + AND_OPERATION(MEMORY_READ_IX()); +} + +/** 31 : AND - Logical AND **/ +INSTRUCTION(ANDiY) +{ + TRACEi(("AND ($%02x),Y", cpu->memory_opcode_read(cpu->reg_PC) )); + AND_OPERATION(MEMORY_READ_IY()); +} + +/** 2D : AND - Logical AND **/ +INSTRUCTION(ANDaB) +{ + TRACEi(("AND $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + AND_OPERATION(MEMORY_READ_AB()); +} + +/** 3D : AND - Logical AND **/ +INSTRUCTION(ANDaX) +{ + TRACEi(("AND $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + AND_OPERATION(MEMORY_READ_AX()); +} + +/** 39 : AND - Logical AND **/ +INSTRUCTION(ANDaY) +{ + TRACEi(("AND $%02x%02x,Y", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + AND_OPERATION(MEMORY_READ_AY()); +} + +/*** Misc instructions ***/ + +/** 24 : BIT **/ +INSTRUCTION(BITzP) +{ + TRACEi(("BIT $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + BIT_OPERATION(MEMORY_READ_ZP()); +} + +/** 2C : BIT **/ +INSTRUCTION(BITaB) +{ + TRACEi(("BIT $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + BIT_OPERATION(MEMORY_READ_AB()); +} + +/** 2A : ROL A **/ +INSTRUCTION(ROLiM) +{ + TRACEi(("ROL A")); + ROL_OPERATION(cpu->reg_A); +} + +/** 6A : ROR A **/ +INSTRUCTION(RORiM) +{ + TRACEi(("ROR A")); + ROR_OPERATION(cpu->reg_A); +} + +/** 0A : ASL A **/ +INSTRUCTION(ASLiM) +{ + TRACEi(("ASL A")); + ASL_OPERATION(cpu->reg_A); +} + +/** 4A : LSR A **/ +INSTRUCTION(LSRiM) +{ + TRACEi(("LSR A")); + LSR_OPERATION(cpu->reg_A); +} + +/** 2E : ROL **/ +INSTRUCTION(ROLaB) +{ + TRACEi(("ROL $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + ROL_OPERATION(val); + MEMORY_WRITE_AB(val); +} + +/** 26 : ROL **/ +INSTRUCTION(ROLzP) +{ + TRACEi(("ROL $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + ROL_OPERATION(val); + MEMORY_WRITE_ZP(val); +} + +/** 3E : ROL **/ +INSTRUCTION(ROLaX) +{ + TRACEi(("ROL $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + ROL_OPERATION(val); + MEMORY_WRITE_AX(val); +} + +/** 36 : ROL **/ +INSTRUCTION(ROLzX) +{ + TRACEi(("ROL $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + ROL_OPERATION(val); + MEMORY_WRITE_ZX(val); +} + +/** 6E : ROR **/ +INSTRUCTION(RORaB) +{ + TRACEi(("ROR $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + ROR_OPERATION(val); + MEMORY_WRITE_AB(val); +} + +/** 66 : ROR **/ +INSTRUCTION(RORzP) +{ + TRACEi(("ROR $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + ROR_OPERATION(val); + MEMORY_WRITE_ZP(val); +} + +/** 7E : ROR **/ +INSTRUCTION(RORaX) +{ + TRACEi(("ROR $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + ROR_OPERATION(val); + MEMORY_WRITE_AX(val); +} + +/** 76 : ROR **/ +INSTRUCTION(RORzX) +{ + TRACEi(("ROR $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + ROR_OPERATION(val); + MEMORY_WRITE_ZX(val); +} + +/** 0E : ASL **/ +INSTRUCTION(ASLaB) +{ + TRACEi(("ASL $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + ASL_OPERATION(val); + MEMORY_WRITE_AB(val); +} + +/** 06 : ASL **/ +INSTRUCTION(ASLzP) +{ + TRACEi(("ASL $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + ASL_OPERATION(val); + MEMORY_WRITE_ZP(val); +} + +/** 1E : ASL **/ +INSTRUCTION(ASLaX) +{ + TRACEi(("ASL $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + ASL_OPERATION(val); + MEMORY_WRITE_AX(val); +} + +/** 16 : ASL **/ +INSTRUCTION(ASLzX) +{ + TRACEi(("ASL $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + ASL_OPERATION(val); + MEMORY_WRITE_ZX(val); +} + +/** 4E : LSR **/ +INSTRUCTION(LSRaB) +{ + TRACEi(("LSR $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + LSR_OPERATION(val); + MEMORY_WRITE_AB(val); +} + +/** 46 : LSR **/ +INSTRUCTION(LSRzP) +{ + TRACEi(("LSR $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + LSR_OPERATION(val); + MEMORY_WRITE_ZP(val); +} + +/** 5E : LSR **/ +INSTRUCTION(LSRaX) +{ + TRACEi(("LSR $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + LSR_OPERATION(val); + MEMORY_WRITE_AX(val); +} + +/** 56 : LSR **/ +INSTRUCTION(LSRzX) +{ + TRACEi(("LSR $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + LSR_OPERATION(val); + MEMORY_WRITE_ZX(val); +} + +/** CE : DEC **/ +INSTRUCTION(DECaB) +{ + TRACEi(("DEC $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + MEMORY_WRITE_AB(--val); + NZ_FLAG_UPDATE(val); +} + +/** C6 : DEC **/ +INSTRUCTION(DECzP) +{ + TRACEi(("DEC $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + MEMORY_WRITE_ZP(--val); + NZ_FLAG_UPDATE(val); +} + +/** DE : DEC **/ +INSTRUCTION(DECaX) +{ + TRACEi(("DEC $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + MEMORY_WRITE_AX(--val); + NZ_FLAG_UPDATE(val); +} + +/** D6 : DEC **/ +INSTRUCTION(DECzX) +{ + TRACEi(("DEC $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + MEMORY_WRITE_ZX(--val); + NZ_FLAG_UPDATE(val); +} + +/** EE : INC **/ +INSTRUCTION(INCaB) +{ + TRACEi(("INC $%02x%02x", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AB(); + cpu->reg_PC -= 2; + MEMORY_WRITE_AB(++val); + NZ_FLAG_UPDATE(val); +} + +/** E6 : INC **/ +INSTRUCTION(INCzP) +{ + TRACEi(("INC $%02x", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZP(); + cpu->reg_PC -= 1; + MEMORY_WRITE_ZP(++val); + NZ_FLAG_UPDATE(val); +} + +/** FE : INC **/ +INSTRUCTION(INCaX) +{ + TRACEi(("INC $%02x%02x,X", cpu->memory_opcode_read(cpu->reg_PC+1), cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_AX(); + cpu->reg_PC -= 2; + MEMORY_WRITE_AX(++val); + NZ_FLAG_UPDATE(val); +} + +/** F6 : INC **/ +INSTRUCTION(INCzX) +{ + TRACEi(("INC $%02x,X", cpu->memory_opcode_read(cpu->reg_PC))); + byte val = MEMORY_READ_ZX(); + cpu->reg_PC -= 1; + MEMORY_WRITE_ZX(++val); + NZ_FLAG_UPDATE(val); +} + +/* */ +static InstructionFunction InstructionTable[256] = +{ +/* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F */ +/* 00 */ I_BRKiM, I_ORAiX, I_ILLEG, I_ILLEG, I_ILLEG, I_ORAzP, I_ASLzP, I_ILLEG, I_PHPiM, I_ORAiM, I_ASLiM, I_ILLEG, I_ILLEG, I_ORAaB, I_ASLaB, I_ILLEG, +/* 10 */ I_BPLrE, I_ORAiY, I_ILLEG, I_ILLEG, I_ILLEG, I_ORAzX, I_ASLzX, I_ILLEG, I_CLCiM, I_ORAaY, I_ILLEG, I_ILLEG, I_ILLEG, I_ORAaX, I_ASLaX, I_ILLEG, +/* 20 */ I_JSRaB, I_ANDiX, I_ILLEG, I_ILLEG, I_BITzP, I_ANDzP, I_ROLzP, I_ILLEG, I_PLPiM, I_ANDiM, I_ROLiM, I_ILLEG, I_BITaB, I_ANDaB, I_ROLaB, I_ILLEG, +/* 30 */ I_BMIrE, I_ANDiY, I_ILLEG, I_ILLEG, I_ILLEG, I_ANDzX, I_ROLzX, I_ILLEG, I_SECiM, I_ANDaY, I_ILLEG, I_ILLEG, I_ILLEG, I_ANDaX, I_ROLaX, I_ILLEG, +/* 40 */ I_RTIiM, I_EORiX, I_ILLEG, I_ILLEG, I_ILLEG, I_EORzP, I_LSRzP, I_ILLEG, I_PHAiM, I_EORiM, I_LSRiM, I_ILLEG, I_JMPaB, I_EORaB, I_LSRaB, I_ILLEG, +/* 50 */ I_BVCrE, I_EORiY, I_ILLEG, I_ILLEG, I_ILLEG, I_EORzX, I_LSRzX, I_ILLEG, I_CLIiM, I_EORaY, I_ILLEG, I_ILLEG, I_ILLEG, I_EORaX, I_LSRaX, I_ILLEG, +/* 60 */ I_RTSiM, I_ADCiX, I_ILLEG, I_ILLEG, I_ILLEG, I_ADCzP, I_RORzP, I_ILLEG, I_PLAiM, I_ADCiM, I_RORiM, I_ILLEG, I_JMPiD, I_ADCaB, I_RORaB, I_ILLEG, +/* 70 */ I_BVSrE, I_ADCiY, I_ILLEG, I_ILLEG, I_ILLEG, I_ADCzX, I_RORzX, I_ILLEG, I_SEIiM, I_ADCaY, I_ILLEG, I_ILLEG, I_ILLEG, I_ADCaX, I_RORaX, I_ILLEG, +/* 80 */ I_ILLEG, I_STAiX, I_ILLEG, I_ILLEG, I_STYzP, I_STAzP, I_STXzP, I_ILLEG, I_DEYiM, I_ILLEG, I_TXAiM, I_ILLEG, I_STYaB, I_STAaB, I_STXaB, I_ILLEG, +/* 90 */ I_BCCrE, I_STAiY, I_ILLEG, I_ILLEG, I_STYzX, I_STAzX, I_STXzY, I_ILLEG, I_TYAiM, I_STAaY, I_TXSiM, I_ILLEG, I_ILLEG, I_STAaX, I_ILLEG, I_ILLEG, +/* A0 */ I_LDYiM, I_LDAiX, I_LDXiM, I_ILLEG, I_LDYzP, I_LDAzP, I_LDXzP, I_ILLEG, I_TAYiM, I_LDAiM, I_TAXiM, I_ILLEG, I_LDYaB, I_LDAaB, I_LDXaB, I_ILLEG, +/* B0 */ I_BCSrE, I_LDAiY, I_ILLEG, I_ILLEG, I_LDYzX, I_LDAzX, I_LDXzY, I_ILLEG, I_CLViM, I_LDAaY, I_TSXiM, I_ILLEG, I_LDYaX, I_LDAaX, I_LDXaY, I_ILLEG, +/* C0 */ I_CPYiM, I_CMPiX, I_ILLEG, I_ILLEG, I_CPYzP, I_CMPzP, I_DECzP, I_ILLEG, I_INYiM, I_CMPiM, I_DEXiM, I_ILLEG, I_CPYaB, I_CMPaB, I_DECaB, I_ILLEG, +/* D0 */ I_BNErE, I_CMPiY, I_ILLEG, I_ILLEG, I_ILLEG, I_CMPzX, I_DECzX, I_ILLEG, I_CLDiM, I_CMPaY, I_ILLEG, I_ILLEG, I_ILLEG, I_CMPaX, I_DECaX, I_ILLEG, +/* E0 */ I_CPXiM, I_SBCiX, I_ILLEG, I_ILLEG, I_CPXzP, I_SBCzP, I_INCzP, I_ILLEG, I_INXiM, I_SBCiM, I_NOPiM, I_ILLEG, I_CPXaB, I_SBCaB, I_INCaB, I_ILLEG, +/* F0 */ I_BEQrE, I_SBCiY, I_ILLEG, I_ILLEG, I_ILLEG, I_SBCzX, I_INCzX, I_ILLEG, I_SEDiM, I_SBCaY, I_ILLEG, I_ILLEG, I_ILLEG, I_SBCaX, I_INCaX, I_ILLEG +/* 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F */ +}; + + +static inline int quick6502_exec_one(quick6502_cpu *cpu) +{ + register byte opcode = cpu->memory_opcode_read(cpu->reg_PC++); + + InstructionTable[opcode](cpu); +#if 0 + TRACEi(("A:%02x X:%02x Y:%02x S:%04x, PC:%04x Flags:[%c%c%c%c%c%c%c%c], Stack[%2.2x, %2.2x, %2.2x]", + cpu->reg_A, cpu->reg_X, cpu->reg_Y, (0x100+cpu->reg_S), cpu->reg_PC, + cpu->reg_P&Q6502_N_FLAG ? 'N':'.', + cpu->reg_P&Q6502_V_FLAG ? 'V':'.', + cpu->reg_P&Q6502_R_FLAG ? 'R':'.', /* No real flag here */ + cpu->reg_P&Q6502_B_FLAG ? 'B':'.', + cpu->reg_P&Q6502_D_FLAG ? 'D':'.', + cpu->reg_P&Q6502_I_FLAG ? 'I':'.', + cpu->reg_P&Q6502_Z_FLAG ? 'Z':'.', + cpu->reg_P&Q6502_C_FLAG ? 'C':'.', + cpu->memory_stack_read (0x100 | (cpu->reg_S+1)), + cpu->memory_stack_read (0x100 | (cpu->reg_S+2)), + cpu->memory_stack_read (0x100 | (cpu->reg_S+3)) + + )); +#endif + + TRACEi(("A:%02x X:%02x Y:%02x S:%04x, PC:%04x Flags:[%c%c%c%c%c%c%c%c],", + cpu->reg_A, cpu->reg_X, cpu->reg_Y, (0x100+cpu->reg_S), cpu->reg_PC, + cpu->reg_P&Q6502_N_FLAG ? 'N':'.', + cpu->reg_P&Q6502_V_FLAG ? 'V':'.', + cpu->reg_P&Q6502_R_FLAG ? 'R':'.', /* No real flag here */ + cpu->reg_P&Q6502_B_FLAG ? 'B':'.', + cpu->reg_P&Q6502_D_FLAG ? 'D':'.', + cpu->reg_P&Q6502_I_FLAG ? 'I':'.', + cpu->reg_P&Q6502_Z_FLAG ? 'Z':'.', + cpu->reg_P&Q6502_C_FLAG ? 'C':'.' + + )); + + cpu->cycle_done += CycleTable[opcode]; + + return 0; +} diff --git a/tools/corecompare/src/CPU_MTO/corecpu.h b/tools/corecompare/src/CPU_MTO/corecpu.h new file mode 100755 index 0000000..2474bea --- /dev/null +++ b/tools/corecompare/src/CPU_MTO/corecpu.h @@ -0,0 +1,163 @@ +/** + * CoreCPU - The Quick6502 Project + * corecpu.h + * + * Created by Manoel Trapier on 24/02/08 + * Copyright 2008 986 Corp. All rights reserved. + * + * $LastChangedDate: 2008-03-21 01:55:10 +0100 (Ven, 21 mar 2008) $ + * $Author: godzil $ + * $HeadURL: svn+ssh://godzil@trac.godzil.net/svn/projects/Quick6502/trunk/corecpu.h $ + * $Revision: 41 $ + * + */ + +#ifndef _QUICK6502_CORECPU_H_ +#define _QUICK6502_CORECPU_H_ + +/* M6502 configuration + * + * Supported DEFINEs : + * NO_DECIMAL Quick6502 will not support BDC arithemtic (used for NES) + * CMOS_6502 Quick6502 will act as a CMOS 6502 (Not actually used) + * + */ + +#ifdef CMOS_6502 +#warning Quick6502 CMOS support is actually desactivated, desactivate it +#undef CMOS_6502 +#endif + +#ifndef NO_DECIMAL +#warning Quick6502 have actually no BCD support, fallback to no NO_DECIMAL +#define NO_DECIMAL +#endif + + +#include "types.h" + +typedef byte (*quick6502_MemoryReadFunction)(unsigned short addr); +typedef void (*quick6502_MemoryWriteFunction)(unsigned short addr, byte value); + +typedef struct quick6502_cpu_ +{ + /* 6502 registers */ + byte reg_A, reg_X, reg_Y; + byte reg_P, reg_S; + unsigned short reg_PC; + + /* Read/Write memory functions */ + quick6502_MemoryReadFunction memory_read; + quick6502_MemoryWriteFunction memory_write; + quick6502_MemoryReadFunction memory_page0_read; + quick6502_MemoryWriteFunction memory_page0_write; + quick6502_MemoryReadFunction memory_stack_read; + quick6502_MemoryWriteFunction memory_stack_write; + quick6502_MemoryReadFunction memory_opcode_read; + + /* Timing related */ + long cycle_done; + byte exit_loop; + + /* Other config options */ + byte running; /* This field is used to prevent cpu free if this cpu is running */ + +} quick6502_cpu; + +typedef struct quick6502_cpuconfig_ +{ + /* Read/Write memory functions */ + quick6502_MemoryReadFunction memory_read; + quick6502_MemoryWriteFunction memory_write; + quick6502_MemoryReadFunction memory_page0_read; + quick6502_MemoryWriteFunction memory_page0_write; + quick6502_MemoryReadFunction memory_stack_read; + quick6502_MemoryWriteFunction memory_stack_write; + quick6502_MemoryReadFunction memory_opcode_read; +} quick6502_cpuconfig; + +/*** Signal that we can send to the CPU ***/ +typedef enum +{ + Q6502_NO_SIGNAL = 0, + Q6502_IRQ_SIGNAL, + Q6502_NMI_SIGNAL, + Q6502_STOPLOOP_SIGNAL +} quick6502_signal; + +/*** Some 6502 related definitions ***/ + +/*** P register flags ***/ +#define Q6502_N_FLAG 0x80 /* Negavite flag */ +#define Q6502_V_FLAG 0x40 /* oVerflow flag */ +#define Q6502_R_FLAG 0x20 /* Not a real flag, but need to be to 1 on PHP */ +#define Q6502_B_FLAG 0x10 /* Break flag */ +#define Q6502_D_FLAG 0x08 /* BCD flag */ +#define Q6502_I_FLAG 0x04 /* IRQ/BRK flag */ +#define Q6502_Z_FLAG 0x02 /* Zero flag */ +#define Q6502_C_FLAG 0x01 /* Carry flag */ + +/*** Interuption Vectors ***/ +#define Q6502_NMI_LOW 0xFFFA +#define Q6502_NMI_HIGH 0xFFFB +#define Q6502_RESET_LOW 0xFFFC +#define Q6502_RESET_HIGH 0xFFFD +#define Q6502_IRQ_LOW 0xFFFE +#define Q6502_IRQ_HIGH 0xFFFF + +/** + * Initialise the CPU + * + * Inputs: + * + * - CPU Init structure: + * +- Memory Read function pointer + * +- Memory Write function pointer + * +- Fast memory read function pointer (for opcodes read) + * +- Fast page 0 function / Read/Write + * +- Fast page 1 function / Read/Write + * + * Output: + * + * (void *): An opaque pointer to the internal structure of the CPU + * + */ +quick6502_cpu *quick6502_init(quick6502_cpuconfig *config); + +/* Reset the CPU (must be done after init) */ +void quick6502_reset(quick6502_cpu *cpu); + +/** + * Run cpu for at least X cycles + * + * Output: + * + * int: (Number of cycle really done) - (Number of cycle asked) + */ +int quick6502_run(quick6502_cpu *cpu, int cycles); + +/** Loop CPU until explicit quit */ +void quick6502_loop(quick6502_cpu *cpu); + +/** Run CPU for one instruction */ +void quick6502_exec(quick6502_cpu *cpu); + +/** Send IRQ/NMI/EXITLOOP signal to CPU */ +void quick6502_int(quick6502_cpu *cpu, quick6502_signal signal); + +/** Dump CPU State to the given file */ +void quick6502_dump(quick6502_cpu *cpu, FILE * fp); + +/** Get current instruction name at specified address and put it into buffer */ +void quick6502_getinstruction(quick6502_cpu *cpu, unsigned short addr, char *buffer); + +/** + * Free the CPU + * + * This function will free the CPU only if it's not currently used, it will + * return !0 if everything goes well and 0 if the free is impossible + */ +int quick6502_free(quick6502_cpu *cpu); + +#endif /* _QUICK6502_CORECPU_H_ */ + diff --git a/tools/corecompare/src/corecompare.c b/tools/corecompare/src/corecompare.c new file mode 100755 index 0000000..f87f6b6 --- /dev/null +++ b/tools/corecompare/src/corecompare.c @@ -0,0 +1,220 @@ +/* + * corecompare.c + * Quick6502 + * + * Created by Manoël Trapier on 18/03/08. + * Copyright 2008 986 Corp. All rights reserved. + * + * Simple tool to compare both core results + * + */ + + +#include +#include +#include + +#include + +#include "corecpu.h" + +#define BLANK_TIME 5000 + +#include "types.h" + +byte mMainMemory[64*1024]; +byte qMainMemory[64*1024]; + +unsigned short ProgramOrg = 0xFFE5; + +byte Program[] = { 0xA9, 0xA5, 0x40, 0x18, 0x78, 0xD8, 0xB8, 0x00, 0xEA, 0xAA, 0xCA, 0xCA, 0xEA, 0x6A, 0x4C, 0xF2, 0xFF, 0xEA, 0x4C, 0xF2, 0xFF, 0xE7, 0xFF, 0xE8, 0xFF, 0xE5, 0xFF }; + +unsigned short Smb1Org = 0x8000; +#include "smb1.h" +#include "nestest.h" + +unsigned short qMemoryReadAddr, mMemoryReadAddr; +unsigned short qMemoryWriteAddr, mMemoryWriteAddr; +unsigned char qMemoryWriteValue, mMemoryWriteValue; +unsigned char qMemoryReadValue, mMemoryReadValue; + +/* Quick6502 related functions and main thread */ + +byte ReadMemory(unsigned short addr) +{ + return (qMemoryReadValue = qMainMemory[(qMemoryReadAddr = addr)]); +} + +byte ReadMemoryOpCode(unsigned short addr) +{ + return qMainMemory[addr] ; +} + +void WriteMemory(unsigned short addr, byte value) +{ + qMemoryWriteValue = value; + qMemoryWriteAddr = addr; + qMainMemory[addr] = value; +} + + +/* JBN's 6502 CPU related functions */ +#include + +#include "cpu6502.h" +#include "cyclesTable.h" + +void Wr6502(register uint16_t Addr,register uint8_t Value) +{ + mMemoryWriteValue = Value; + mMemoryWriteAddr = Addr; + mMainMemory[Addr] = Value; +} + +uint8_t Rd6502 (register uint16_t Addr) +{ + return (mMemoryReadValue = mMainMemory[(mMemoryReadAddr = Addr)]); +} + +uint8_t Op6502 (register uint16_t Addr) +{ + return mMainMemory[Addr]; +} + +void debugger_stop () +{ + +} + +int Exec6502 (nes_cpu6502_t *cpu) +{ + uint8_t opcode; + int result; + + /* Manage the Current Opcode. */ + opcode = cpu->memRead (cpu->pc); + result = cpu6502_execOpCode (cpu, opcode); + if (result != 0) { + return -1; + } + + /* Compute the CPU Time taken by the executed opcode. */ + cpu->nbCycles -= OpcodesCycles[opcode]; + return result; +} + +int main (int argc, const char * argv[]) { + char qBuffer[100], + mBuffer[100], + qBuffer2[100], + mBuffer2[100]; + int result, result2; + int count = 0; + int x; + /* Copy the 6502 program to both CPU's Memory */ + //memcpy(MainMemory+ ProgramOrg, Program, 0x10000 - ProgramOrg ); + + //memcpy(qMainMemory+ Smb1Org, smb1, 0x10000 - Smb1Org ); + //memcpy(mMainMemory+ Smb1Org, smb1, 0x10000 - Smb1Org ); + + memcpy(qMainMemory+ 0xC000, nestest, 0x10000 - 0xC000 ); + memcpy(mMainMemory+ 0xC000, nestest, 0x10000 - 0xC000 ); + + mMainMemory[0x2002] = 0xC0; + qMainMemory[0x2002] = 0xC0; + +/* mMainMemory[0x4016] = 0x41; + qMainMemory[0x4016] = 0x41;*/ + + /* Initialise both core */ + nes_cpu6502_t mCpu; + quick6502_cpu *qCpu; + quick6502_cpuconfig CpuConfig; + + /* Init the CPU */ + CpuConfig.memory_read = ReadMemory; + CpuConfig.memory_write = WriteMemory; + + CpuConfig.memory_opcode_read = ReadMemory; + CpuConfig.memory_page0_read = + CpuConfig.memory_stack_read = NULL; + CpuConfig.memory_page0_write = + CpuConfig.memory_stack_write = NULL; + + qCpu = quick6502_init(&CpuConfig); + if (!qCpu) + { + printf("CPU initialisation error..."); + exit(-1); + } + + + mCpu.memRead = Rd6502; + mCpu.memWrite = Wr6502; + + quick6502_reset(qCpu); + + cpuReset (&mCpu); + + /* Run each one insruction by one instruction */ + while(1) + { + if (count > 19000) + { + printf("Fire NMI!\n"); + quick6502_int(qCpu, Q6502_NMI_SIGNAL); + NMI_Interrupt (&mCpu); + count = 0; + } + + mMemoryWriteValue = 0; + mMemoryWriteAddr = 0; + mMemoryReadValue = 0; + mMemoryReadAddr = 0; + + qMemoryWriteValue = 0; + qMemoryWriteAddr = 0; + qMemoryReadValue = 0; + qMemoryReadAddr = 0; + + quick6502_exec(qCpu); + Exec6502(&mCpu); + sprintf(qBuffer, "A:%02X X:%02X Y:%02X S:%02X P:%02X PC:%04X", + qCpu->reg_A, qCpu->reg_X, qCpu->reg_Y, qCpu->reg_S, qCpu->reg_P, qCpu->reg_PC); + + sprintf(mBuffer, "A:%02X X:%02X Y:%02X S:%02X P:%02X PC:%04X", + mCpu.a, mCpu.x, mCpu.y, mCpu.R_Stack, mCpu.R_Status, mCpu.pc); + + result = strcmp(qBuffer, mBuffer); + sprintf(qBuffer2, "[R:%04X:%02X - W:%04X:%02X]", + qMemoryReadAddr, + qMemoryReadValue, + qMemoryWriteAddr, + qMemoryWriteValue); + + sprintf(mBuffer2, "[R:%04X:%02X - W:%04X:%02X]", + mMemoryReadAddr, + mMemoryReadValue, + mMemoryWriteAddr, + mMemoryWriteValue); + result2 = strcmp(qBuffer2, mBuffer2); + + if ((result != 0) || (result2 != 0)) + { +#if 0 + for ( x = 0x00; x < 0x100; x++) + { + printf("%02X|%02X ", ReadMemory(x), Rd6502(x)); + if ((x&0x0F) == 0x0F) + printf("\n"); + } +#endif + printf("REGS | %s | %s | %s\n", qBuffer, (result==0)?"===":"/!\\", mBuffer); + printf("MEMA | %s | %s | %s\n", qBuffer2, (result2==0)?"===":"/!\\", mBuffer2); + } + count ++; + } + + + return 0; +} diff --git a/tools/corecompare/src/include/nestest.h b/tools/corecompare/src/include/nestest.h new file mode 100755 index 0000000..2104790 --- /dev/null +++ b/tools/corecompare/src/include/nestest.h @@ -0,0 +1,2240 @@ +/* Generated data file from file 'stdin' */ + + +unsigned char nestest[] = { + 0x4C, 0xF5, 0xC5, 0x60, 0x78, 0xD8, \ + 0xA2, 0xFF, 0x9A, 0xAD, 0x02, 0x20, 0x10, 0xFB, 0xAD, 0x02, 0x20, \ + 0x10, 0xFB, 0xA9, 0x00, 0x8D, 0x00, 0x20, 0x8D, 0x01, 0x20, 0x8D, \ + 0x05, 0x20, 0x8D, 0x05, 0x20, 0xAD, 0x02, 0x20, 0xA2, 0x20, 0x8E, \ + 0x06, 0x20, 0xA2, 0x00, 0x8E, 0x06, 0x20, 0xA2, 0x00, 0xA0, 0x0F, \ + 0xA9, 0x00, 0x8D, 0x07, 0x20, 0xCA, 0xD0, 0xFA, 0x88, 0xD0, 0xF7, \ + 0xA9, 0x3F, 0x8D, 0x06, 0x20, 0xA9, 0x00, 0x8D, 0x06, 0x20, 0xA2, \ + 0x00, 0xBD, 0x78, 0xFF, 0x8D, 0x07, 0x20, 0xE8, 0xE0, 0x20, 0xD0, \ + 0xF5, 0xA9, 0xC0, 0x8D, 0x17, 0x40, 0xA9, 0x00, 0x8D, 0x15, 0x40, \ + 0xA9, 0x78, 0x85, 0xD0, 0xA9, 0xFB, 0x85, 0xD1, 0xA9, 0x7F, 0x85, \ + 0xD3, 0xA0, 0x00, 0x8C, 0x06, 0x20, 0x8C, 0x06, 0x20, 0xA9, 0x00, \ + 0x85, 0xD7, 0xA9, 0x07, 0x85, 0xD0, 0xA9, 0xC3, 0x85, 0xD1, 0x20, \ + 0xA7, 0xC2, 0x20, 0x8D, 0xC2, 0xA2, 0x12, 0x20, 0x61, 0xC2, 0xA5, \ + 0xD5, 0x4A, 0x4A, 0x4A, 0xB0, 0x1C, 0x4A, 0xB0, 0x0C, 0x4A, 0xB0, \ + 0x27, 0x4A, 0xB0, 0x03, 0x4C, 0x81, 0xC0, 0x4C, 0x26, 0xC1, 0x20, \ + 0x6F, 0xC6, 0xC6, 0xD7, 0x10, 0xDB, 0xA9, 0x0D, 0x85, 0xD7, 0xD0, \ + 0xD5, 0x20, 0x6F, 0xC6, 0xE6, 0xD7, 0xA5, 0xD7, 0xC9, 0x0E, 0x90, \ + 0xCA, 0xA9, 0x00, 0x85, 0xD7, 0xF0, 0xC4, 0x20, 0x89, 0xC6, 0xA5, \ + 0xD7, 0xF0, 0x06, 0x20, 0xED, 0xC0, 0x4C, 0x81, 0xC0, 0xA9, 0x00, \ + 0x85, 0xD8, 0xE6, 0xD7, 0x20, 0xED, 0xC0, 0xE6, 0xD7, 0xA5, 0xD7, \ + 0xC9, 0x0E, 0xD0, 0xF5, 0xA9, 0x00, 0x85, 0xD7, 0xA5, 0xD8, 0xF0, \ + 0x02, 0xA9, 0xFF, 0x85, 0x00, 0x20, 0xED, 0xC1, 0x4C, 0x81, 0xC0, \ + 0xA5, 0xD7, 0x0A, 0xAA, 0xBD, 0x0A, 0xC1, 0x8D, 0x00, 0x02, 0xBD, \ + 0x0B, 0xC1, 0x8D, 0x01, 0x02, 0xA9, 0xC1, 0x48, 0xA9, 0xDE, 0x48, \ + 0xA9, 0x00, 0x85, 0x00, 0x6C, 0x00, 0x02, 0x2D, 0xC7, 0x2D, 0xC7, \ + 0xDB, 0xC7, 0x85, 0xC8, 0xDE, 0xCB, 0xF8, 0xCD, 0xEE, 0xCE, 0xA2, \ + 0xCF, 0x74, 0xD1, 0xFB, 0xD4, 0xD4, 0xC1, 0x4A, 0xDF, 0xB8, 0xDB, \ + 0xAA, 0xE1, 0xA9, 0x00, 0x85, 0xD7, 0xA9, 0x92, 0x85, 0xD0, 0xA9, \ + 0xC4, 0x85, 0xD1, 0x20, 0xA7, 0xC2, 0x20, 0x8D, 0xC2, 0xA2, 0x0F, \ + 0x20, 0x61, 0xC2, 0xA5, 0xD5, 0x4A, 0x4A, 0x4A, 0xB0, 0x1C, 0x4A, \ + 0xB0, 0x0C, 0x4A, 0xB0, 0x27, 0x4A, 0xB0, 0x03, 0x4C, 0x35, 0xC1, \ + 0x4C, 0x72, 0xC0, 0x20, 0x6F, 0xC6, 0xC6, 0xD7, 0x10, 0xDB, 0xA9, \ + 0x0A, 0x85, 0xD7, 0xD0, 0xD5, 0x20, 0x6F, 0xC6, 0xE6, 0xD7, 0xA5, \ + 0xD7, 0xC9, 0x0B, 0x90, 0xCA, 0xA9, 0x00, 0x85, 0xD7, 0xF0, 0xC4, \ + 0x20, 0x89, 0xC6, 0xA5, 0xD7, 0xF0, 0x06, 0x20, 0xA1, 0xC1, 0x4C, \ + 0x35, 0xC1, 0xA9, 0x00, 0x85, 0xD8, 0xE6, 0xD7, 0x20, 0xA1, 0xC1, \ + 0xE6, 0xD7, 0xA5, 0xD7, 0xC9, 0x0B, 0xD0, 0xF5, 0xA9, 0x00, 0x85, \ + 0xD7, 0xA5, 0xD8, 0xF0, 0x02, 0xA9, 0xFF, 0x85, 0x00, 0x20, 0xED, \ + 0xC1, 0x4C, 0x35, 0xC1, 0xA5, 0xD7, 0x0A, 0xAA, 0xBD, 0xBE, 0xC1, \ + 0x8D, 0x00, 0x02, 0xBD, 0xBF, 0xC1, 0x8D, 0x01, 0x02, 0xA9, 0xC1, \ + 0x48, 0xA9, 0xDE, 0x48, 0xA9, 0x00, 0x85, 0x00, 0x6C, 0x00, 0x02, \ + 0xA3, 0xC6, 0xA3, 0xC6, 0x1E, 0xE5, 0x3D, 0xE7, 0xD3, 0xE8, 0x16, \ + 0xE9, 0x86, 0xEB, 0xF6, 0xED, 0x66, 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0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; diff --git a/tools/corecompare/src/include/smb1.h b/tools/corecompare/src/include/smb1.h new file mode 100755 index 0000000..e7dfd5e --- /dev/null +++ b/tools/corecompare/src/include/smb1.h @@ -0,0 +1,3730 @@ +/* Generated data file from file 'stdin' */ + + +unsigned char smb1[] = { + 0x78, 0xD8, 0xA9, 0x40, 0x8D, 0x00, \ + 0x20, 0xA2, 0xFF, 0x9A, 0xAD, 0x02, 0x20, 0x10, 0xFB, 0xAD, 0x02, \ + 0x20, 0x10, 0xFB, 0xA0, 0xFE, 0xA2, 0x05, 0xBD, 0xD7, 0x07, 0xC9, \ + 0x0A, 0xB0, 0x0C, 0xCA, 0x10, 0xF6, 0xAD, 0xFF, 0x07, 0xC9, 0xA5, \ + 0xD0, 0x02, 0xA0, 0xD6, 0x20, 0xCC, 0x90, 0x8D, 0x11, 0x40, 0x8D, \ + 0x70, 0x07, 0xA9, 0xA5, 0x8D, 0xFF, 0x07, 0x8D, 0xA7, 0x07, 0xA9, \ + 0x0F, 0x8D, 0x15, 0x40, 0xA9, 0x06, 0x8D, 0x01, 0x20, 0x20, 0x20, \ + 0x82, 0x20, 0x19, 0x8E, 0xEE, 0x74, 0x07, 0xAD, 0x78, 0x07, 0x09, \ + 0x80, 0x20, 0xED, 0x8E, 0x4C, 0x57, 0x80, 0x01, 0xA4, 0xC8, 0xEC, \ + 0x10, 0x00, 0x41, 0x41, 0x4C, 0x34, 0x3C, 0x44, 0x54, 0x68, 0x7C, \ + 0xA8, 0xBF, 0xDE, 0xEF, 0x03, 0x8C, 0x8C, 0x8C, 0x8D, 0x03, 0x03, \ + 0x03, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, 0x8D, \ + 0x8D, 0x00, 0x40, 0xAD, 0x78, 0x07, 0x29, 0x7F, 0x8D, 0x78, 0x07, \ + 0x29, 0x7E, 0x8D, 0x00, 0x20, 0xAD, 0x79, 0x07, 0x29, 0xE6, 0xAC, \ + 0x74, 0x07, 0xD0, 0x05, 0xAD, 0x79, 0x07, 0x09, 0x1E, 0x8D, 0x79, \ + 0x07, 0x29, 0xE7, 0x8D, 0x01, 0x20, 0xAE, 0x02, 0x20, 0xA9, 0x00, \ + 0x20, 0xE6, 0x8E, 0x8D, 0x03, 0x20, 0xA9, 0x02, 0x8D, 0x14, 0x40, \ + 0xAE, 0x73, 0x07, 0xBD, 0x5A, 0x80, 0x85, 0x00, 0xBD, 0x6D, 0x80, \ + 0x85, 0x01, 0x20, 0xDD, 0x8E, 0xA0, 0x00, 0xAE, 0x73, 0x07, 0xE0, \ + 0x06, 0xD0, 0x01, 0xC8, 0xBE, 0x80, 0x80, 0xA9, 0x00, 0x9D, 0x00, \ + 0x03, 0x9D, 0x01, 0x03, 0x8D, 0x73, 0x07, 0xAD, 0x79, 0x07, 0x8D, \ + 0x01, 0x20, 0x20, 0xD0, 0xF2, 0x20, 0x5C, 0x8E, 0x20, 0x82, 0x81, \ + 0x20, 0x97, 0x8F, 0xAD, 0x76, 0x07, 0x4A, 0xB0, 0x25, 0xAD, 0x47, \ + 0x07, 0xF0, 0x05, 0xCE, 0x47, 0x07, 0xD0, 0x19, 0xA2, 0x14, 0xCE, \ + 0x7F, 0x07, 0x10, 0x07, 0xA9, 0x14, 0x8D, 0x7F, 0x07, 0xA2, 0x23, \ + 0xBD, 0x80, 0x07, 0xF0, 0x03, 0xDE, 0x80, 0x07, 0xCA, 0x10, 0xF5, \ + 0xE6, 0x09, 0xA2, 0x00, 0xA0, 0x07, 0xAD, 0xA7, 0x07, 0x29, 0x02, \ + 0x85, 0x00, 0xAD, 0xA8, 0x07, 0x29, 0x02, 0x45, 0x00, 0x18, 0xF0, \ + 0x01, 0x38, 0x7E, 0xA7, 0x07, 0xE8, 0x88, 0xD0, 0xF9, 0xAD, 0x22, \ + 0x07, 0xF0, 0x1F, 0xAD, 0x02, 0x20, 0x29, 0x40, 0xD0, 0xF9, 0xAD, \ + 0x76, 0x07, 0x4A, 0xB0, 0x06, 0x20, 0x23, 0x82, 0x20, 0xC6, 0x81, \ + 0xAD, 0x02, 0x20, 0x29, 0x40, 0xF0, 0xF9, 0xA0, 0x14, 0x88, 0xD0, \ + 0xFD, 0xAD, 0x3F, 0x07, 0x8D, 0x05, 0x20, 0xAD, 0x40, 0x07, 0x8D, \ + 0x05, 0x20, 0xAD, 0x78, 0x07, 0x48, 0x8D, 0x00, 0x20, 0xAD, 0x76, \ + 0x07, 0x4A, 0xB0, 0x03, 0x20, 0x12, 0x82, 0xAD, 0x02, 0x20, 0x68, \ + 0x09, 0x80, 0x8D, 0x00, 0x20, 0x40, 0xAD, 0x70, 0x07, 0xC9, 0x02, \ + 0xF0, 0x0B, 0xC9, 0x01, 0xD0, 0x38, 0xAD, 0x72, 0x07, 0xC9, 0x03, \ + 0xD0, 0x31, 0xAD, 0x77, 0x07, 0xF0, 0x04, 0xCE, 0x77, 0x07, 0x60, \ + 0xAD, 0xFC, 0x06, 0x29, 0x10, 0xF0, 0x19, 0xAD, 0x76, 0x07, 0x29, \ + 0x80, 0xD0, 0x1A, 0xA9, 0x2B, 0x8D, 0x77, 0x07, 0xAD, 0x76, 0x07, \ + 0xA8, 0xC8, 0x84, 0xFA, 0x49, 0x01, 0x09, 0x80, 0xD0, 0x05, 0xAD, \ + 0x76, 0x07, 0x29, 0x7F, 0x8D, 0x76, 0x07, 0x60, 0xAC, 0x4E, 0x07, \ + 0xA9, 0x28, 0x85, 0x00, 0xA2, 0x0E, 0xBD, 0xE4, 0x06, 0xC5, 0x00, \ + 0x90, 0x0F, 0xAC, 0xE0, 0x06, 0x18, 0x79, 0xE1, 0x06, 0x90, 0x03, \ + 0x18, 0x65, 0x00, 0x9D, 0xE4, 0x06, 0xCA, 0x10, 0xE7, 0xAE, 0xE0, \ + 0x06, 0xE8, 0xE0, 0x03, 0xD0, 0x02, 0xA2, 0x00, 0x8E, 0xE0, 0x06, \ + 0xA2, 0x08, 0xA0, 0x02, 0xB9, 0xE9, 0x06, 0x9D, 0xF1, 0x06, 0x18, \ + 0x69, 0x08, 0x9D, 0xF2, 0x06, 0x18, 0x69, 0x08, 0x9D, 0xF3, 0x06, \ + 0xCA, 0xCA, 0xCA, 0x88, 0x10, 0xE8, 0x60, 0xAD, 0x70, 0x07, 0x20, \ + 0x04, 0x8E, 0x31, 0x82, 0xDC, 0xAE, 0x8B, 0x83, 0x18, 0x92, 0xA0, \ + 0x00, 0x2C, 0xA0, 0x04, 0xA9, 0xF8, 0x99, 0x00, 0x02, 0xC8, 0xC8, \ + 0xC8, 0xC8, 0xD0, 0xF7, 0x60, 0xAD, 0x72, 0x07, 0x20, 0x04, 0x8E, \ + 0xCF, 0x8F, 0x67, 0x85, 0x61, 0x90, 0x45, 0x82, 0x04, 0x20, 0x73, \ + 0x01, 0x00, 0x00, 0xA0, 0x00, 0xAD, 0xFC, 0x06, 0x0D, 0xFD, 0x06, \ + 0xC9, 0x10, 0xF0, 0x04, 0xC9, 0x90, 0xD0, 0x03, 0x4C, 0xD8, 0x82, \ + 0xC9, 0x20, 0xF0, 0x1A, 0xAE, 0xA2, 0x07, 0xD0, 0x0B, 0x8D, 0x80, \ + 0x07, 0x20, 0x6B, 0x83, 0xB0, 0x60, 0x4C, 0xC0, 0x82, 0xA2, 0x01, \ + 0xEA, 0xF0, 0x4A, 0xC9, 0x40, 0xEA, 0xEA, 0xC8, 0xAD, 0xA2, 0x07, \ + 0xF0, 0x4E, 0xA9, 0x18, 0xEA, 0xEA, 0xEA, 0xAD, 0x80, 0x07, 0xD0, \ + 0x36, 0xA9, 0x10, 0x8D, 0x80, 0x07, 0xC0, 0x01, 0xF0, 0x0E, 0xAD, \ + 0x7A, 0x07, 0x49, 0x01, 0x8D, 0x7A, 0x07, 0x20, 0x25, 0x83, 0x4C, \ + 0xBB, 0x82, 0xAE, 0x6B, 0x07, 0xAD, 0x3E, 0x01, 0xEA, 0x20, 0xEA, \ + 0xFF, 0x20, 0x0E, 0x83, 0xBD, 0x3F, 0x82, 0x9D, 0x00, 0x03, 0xE8, \ + 0xE0, 0x06, 0x30, 0xF5, 0xAC, 0x5F, 0x07, 0xC8, 0x8C, 0x04, 0x03, \ + 0xA9, 0x00, 0x8D, 0xFC, 0x06, 0x20, 0xEA, 0xAE, 0xA5, 0x0E, 0xC9, \ + 0x06, 0xD0, 0x44, 0xA9, 0x00, 0x8D, 0x70, 0x07, 0x8D, 0x72, 0x07, \ + 0x8D, 0x22, 0x07, 0xEE, 0x74, 0x07, 0x60, 0xAC, 0xA2, 0x07, 0xF0, \ + 0xEC, 0x0A, 0x90, 0x06, 0xAD, 0xFD, 0x07, 0x20, 0x0E, 0x83, 0x20, \ + 0x03, 0x9C, 0xEE, 0x5D, 0x07, 0xEE, 0x64, 0x07, 0xEE, 0x57, 0x07, \ + 0xEE, 0x70, 0x07, 0xAD, 0xFC, 0x07, 0x8D, 0x6A, 0x07, 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0x22, 0x0E, \ + 0x1B, 0x24, 0x10, 0x0A, 0x16, 0x0E, 0x22, 0x8B, 0x0D, 0x02, 0x24, \ + 0x19, 0x15, 0x0A, 0x22, 0x0E, 0x1B, 0x24, 0x10, 0x0A, 0x16, 0x0E, \ + 0x22, 0xEC, 0x04, 0x1D, 0x18, 0x19, 0x28, 0x22, 0xF6, 0x01, 0x00, \ + 0x23, 0xC9, 0x56, 0x55, 0x23, 0xE2, 0x04, 0x99, 0xAA, 0xAA, 0xAA, \ + 0x23, 0xEA, 0x04, 0x99, 0xAA, 0xAA, 0xAA, 0x00, 0xFF, 0xFF, 0xFF, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xFF + }; diff --git a/tools/corecompare/src/include/types.h b/tools/corecompare/src/include/types.h new file mode 100755 index 0000000..c2d03c6 --- /dev/null +++ b/tools/corecompare/src/include/types.h @@ -0,0 +1,28 @@ +/* + * Base type definitions - The TI-NESulator Project + * types.h - Taken from the Quick6502 project + * + * Created by Manoel Trapier on 18/09/06. + * Copyright 2003-2008 986 Corp. All rights reserved. + * + * $LastChangedDate: 2008-03-12 12:12:07 +0100 (Mer, 12 mar 2008) $ + * $Author: godzil $ + * $HeadURL: svn+ssh://godzil@trac.godzil.net/svn/projects/Quick6502/types.h $ + * $Revision: 26 $ + * + */ + +#ifndef TYPES_H +#define TYPES_H + +#ifndef BYTE_TYPE_DEFINED +#define BYTE_TYPE_DEFINED +typedef unsigned char byte; +#endif + +typedef unsigned char bool; + +#define true (0) +#define false (!true) + +#endif diff --git a/unix/SConstruct b/unix/SConstruct new file mode 100644 index 0000000..d13f7b7 --- /dev/null +++ b/unix/SConstruct @@ -0,0 +1,15 @@ +# -*- python -*- + +############## +# Nes program +# +# + +Program('nes', ['../src/main.c', '../src/debug.c', '../src/cpu/cpu6502.c', + '../src/emulator/emulator.c', '../src/emulator/memory.c', + '../src/emulator/ppu.c', '../src/emulator/apu.c', + '../src/emulator/debugger.c', '../src/emulator/paddle.c'], + CPPPATH=['../src', '../src/cpu', '../src/emulator'], + CCFLAGS='-g -Wall `sdl-config --cflags`', + LIBS=['SDL'], + LIBPATH='/usr/lib')