rpi/domo
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Move all to deprecated folder.

Browse Source
This commit is contained in:
NADAL Jean-Baptiste
2016-11-16 21:57:57 +01:00
parent 01738a7684
commit 05de7d6c04
9777 changed files with 0 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

409
deprecated/firmware/buildroot/arch/Config.in Normal file
View File

@@ -0,0 +1,409 @@
menu "Target options"
config BR2_ARCH_IS_64
bool
config BR2_KERNEL_64_USERLAND_32
bool
config BR2_SOFT_FLOAT
bool
config BR2_ARCH_HAS_MMU_MANDATORY
bool
config BR2_ARCH_HAS_MMU_OPTIONAL
bool
config BR2_ARCH_HAS_FDPIC_SUPPORT
bool
choice
prompt "Target Architecture"
default BR2_i386
help
Select the target architecture family to build for.
config BR2_arcle
bool "ARC (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
that can be used from deeply embedded to high performance host
applications. Little endian.
config BR2_arceb
bool "ARC (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
that can be used from deeply embedded to high performance host
applications. Big endian.
config BR2_arm
bool "ARM (little endian)"
# MMU support is set by the subarchitecture file, arch/Config.in.arm
help
ARM is a 32-bit reduced instruction set computer (RISC) instruction
set architecture (ISA) developed by ARM Holdings. Little endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
config BR2_armeb
bool "ARM (big endian)"
# MMU support is set by the subarchitecture file, arch/Config.in.arm
help
ARM is a 32-bit reduced instruction set computer (RISC) instruction
set architecture (ISA) developed by ARM Holdings. Big endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
config BR2_aarch64
bool "AArch64 (little endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
Aarch64 is a 64-bit architecture developed by ARM Holdings.
http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
http://en.wikipedia.org/wiki/ARM
config BR2_aarch64_be
bool "AArch64 (big endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
Aarch64 is a 64-bit architecture developed by ARM Holdings.
http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
http://en.wikipedia.org/wiki/ARM
config BR2_bfin
bool "Blackfin"
select BR2_ARCH_HAS_FDPIC_SUPPORT
help
The Blackfin is a family of 16 or 32-bit microprocessors developed,
manufactured and marketed by Analog Devices.
http://www.analog.com/
http://en.wikipedia.org/wiki/Blackfin
config BR2_i386
bool "i386"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Intel i386 architecture compatible microprocessor
http://en.wikipedia.org/wiki/I386
config BR2_m68k
bool "m68k"
select BR2_ARCH_HAS_MMU_MANDATORY
depends on BROKEN # ice in uclibc / inet_ntoa_r
help
Motorola 68000 family microprocessor
http://en.wikipedia.org/wiki/M68k
config BR2_microblazeel
bool "Microblaze AXI (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
based architecture (little endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
config BR2_microblazebe
bool "Microblaze non-AXI (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
based architecture (non-AXI, big endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
config BR2_mips
bool "MIPS (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mipsel
bool "MIPS (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mips64
bool "MIPS64 (big endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_mips64el
bool "MIPS64 (little endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
config BR2_nios2
bool "Nios II"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Nios II is a soft core processor from Altera Corporation.
http://www.altera.com/
http://en.wikipedia.org/wiki/Nios_II
config BR2_powerpc
bool "PowerPC"
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_powerpc64
bool "PowerPC64 (big endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_powerpc64le
bool "PowerPC64 (little endian)"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Little endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_sh
bool "SuperH"
select BR2_ARCH_HAS_MMU_OPTIONAL
help
SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by Hitachi.
http://www.hitachi.com/
http://en.wikipedia.org/wiki/SuperH
config BR2_sh64
bool "SuperH64"
depends on BR2_DEPRECATED_SINCE_2015_05
select BR2_ARCH_HAS_MMU_MANDATORY
help
SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by Hitachi.
http://www.hitachi.com/
http://en.wikipedia.org/wiki/SuperH
config BR2_sparc
bool "SPARC"
select BR2_ARCH_HAS_MMU_MANDATORY
help
SPARC (from Scalable Processor Architecture) is a RISC instruction
set architecture (ISA) developed by Sun Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
config BR2_sparc64
bool "SPARC64"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
SPARC (from Scalable Processor Architecture) is a RISC instruction
set architecture (ISA) developed by Sun Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
config BR2_x86_64
bool "x86_64"
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
x86-64 is an extension of the x86 instruction set (Intel i386
architecture compatible microprocessor).
http://en.wikipedia.org/wiki/X86_64
config BR2_xtensa
bool "Xtensa"
# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
help
Xtensa is a Tensilica processor IP architecture.
http://en.wikipedia.org/wiki/Xtensa
http://www.tensilica.com/
endchoice
# The following string values are defined by the individual
# Config.in.$ARCH files
config BR2_ARCH
string
config BR2_ENDIAN
string
config BR2_GCC_TARGET_ARCH
string
config BR2_GCC_TARGET_ABI
string
config BR2_GCC_TARGET_CPU
string
config BR2_GCC_TARGET_CPU_REVISION
string
# The value of this option will be passed as --with-fpu=<value> when
# building gcc (internal backend) or -mfpu=<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_FPU
string
# The value of this option will be passed as --with-float=<value> when
# building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_FLOAT_ABI
string
# The value of this option will be passed as --with-mode=<value> when
# building gcc (internal backend) or -m<value> in the toolchain
# wrapper (external toolchain)
config BR2_GCC_TARGET_MODE
string
# Must be selected by binary formats that support shared libraries.
config BR2_BINFMT_SUPPORTS_SHARED
bool
# Set up target binary format
choice
prompt "Target Binary Format"
default BR2_BINFMT_ELF if BR2_USE_MMU
default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
default BR2_BINFMT_FLAT
config BR2_BINFMT_ELF
bool "ELF"
depends on BR2_USE_MMU
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF (Executable and Linkable Format) is a format for libraries and
executables used across different architectures and operating
systems.
config BR2_BINFMT_FDPIC
bool "FDPIC"
depends on BR2_ARCH_HAS_FDPIC_SUPPORT
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF FDPIC binaries are based on ELF, but allow the individual load
segments of a binary to be located in memory independently of each
other. This makes this format ideal for use in environments where no
MMU is available.
config BR2_BINFMT_FLAT
bool "FLAT"
depends on !BR2_USE_MMU
help
FLAT binary is a relatively simple and lightweight executable format
based on the original a.out format. It is widely used in environment
where no MMU is available.
endchoice
# Set up flat binary type
choice
prompt "FLAT Binary type"
depends on BR2_BINFMT_FLAT
default BR2_BINFMT_FLAT_ONE
config BR2_BINFMT_FLAT_ONE
bool "One memory region"
help
All segments are linked into one memory region.
config BR2_BINFMT_FLAT_SEP_DATA
bool "Separate data and code region"
help
Allow for the data and text segments to be separated and placed in
different regions of memory.
config BR2_BINFMT_FLAT_SHARED
bool "Shared binary"
# Even though this really generates shared binaries, there is no libdl
# and dlopen() cannot be used. So packages that require shared
# libraries cannot be built. Therefore, we don't select
# BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
# Although this adds -static to the compilation, that's not a problem
# because the -mid-shared-library option overrides it.
help
Allow to load and link indiviual FLAT binaries at run time.
endchoice
if BR2_arcle || BR2_arceb
source "arch/Config.in.arc"
endif
if BR2_arm || BR2_armeb
source "arch/Config.in.arm"
endif
if BR2_aarch64 || BR2_aarch64_be
source "arch/Config.in.aarch64"
endif
if BR2_bfin
source "arch/Config.in.bfin"
endif
if BR2_m68k
source "arch/Config.in.m68k"
endif
if BR2_microblazeel || BR2_microblazebe
source "arch/Config.in.microblaze"
endif
if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
source "arch/Config.in.mips"
endif
if BR2_nios2
source "arch/Config.in.nios2"
endif
if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
source "arch/Config.in.powerpc"
endif
if BR2_sh || BR2_sh64
source "arch/Config.in.sh"
endif
if BR2_sparc || BR2_sparc64
source "arch/Config.in.sparc"
endif
if BR2_i386 || BR2_x86_64
source "arch/Config.in.x86"
endif
if BR2_xtensa
source "arch/Config.in.xtensa"
endif
endmenu # Target options

7
deprecated/firmware/buildroot/arch/Config.in.aarch64 Normal file
View File

@@ -0,0 +1,7 @@
config BR2_ARCH
default "aarch64" if BR2_aarch64
default "aarch64_be" if BR2_aarch64_be
config BR2_ENDIAN
default "LITTLE" if BR2_aarch64
default "BIG" if BR2_aarch64_be

77
deprecated/firmware/buildroot/arch/Config.in.arc Normal file
View File

@@ -0,0 +1,77 @@
choice
prompt "Target CPU"
depends on BR2_arc
default BR2_arc770d
help
Specific CPU to use
config BR2_arc750d
bool "ARC 750D"
config BR2_arc770d
bool "ARC 770D"
config BR2_archs38
bool "ARC HS38"
endchoice
# Choice of atomic instructions presence
config BR2_ARC_ATOMIC_EXT
bool "Atomic extension (LLOCK/SCOND instructions)"
default y if BR2_arc770d || BR2_archs38
config BR2_ARCH
default "arc" if BR2_arcle
default "arceb" if BR2_arceb
config BR2_arc
bool
default y if BR2_arcle || BR2_arceb
config BR2_ENDIAN
default "LITTLE" if BR2_arcle
default "BIG" if BR2_arceb
config BR2_GCC_TARGET_CPU
default "arc700" if BR2_arc750d
default "arc700" if BR2_arc770d
default "archs" if BR2_archs38
choice
prompt "MMU Page Size"
default BR2_ARC_PAGE_SIZE_8K
help
MMU starting from version 3 (found in ARC 770) and now
version 4 (found in ARC HS38) allows the selection of the
page size during ASIC design creation.
The following options are available for MMU v3 and v4: 4kB,
8kB and 16 kB.
The default is 8 kB (that really matches the only page size
in MMU v2). It is important to build a toolchain with page
size matching the hardware configuration. Otherwise
user-space applications will fail at runtime.
config BR2_ARC_PAGE_SIZE_4K
bool "4KB"
depends on BR2_arc770d || BR2_archs38
config BR2_ARC_PAGE_SIZE_8K
bool "8KB"
help
This is the one and only option available for MMUv2 and
default value for MMU v3 and v4.
config BR2_ARC_PAGE_SIZE_16K
bool "16KB"
depends on BR2_arc770d || BR2_archs38
endchoice
config BR2_ARC_PAGE_SIZE
string
default "4K" if BR2_ARC_PAGE_SIZE_4K
default "8K" if BR2_ARC_PAGE_SIZE_8K
default "16K" if BR2_ARC_PAGE_SIZE_16K

471
deprecated/firmware/buildroot/arch/Config.in.arm Normal file
View File

@@ -0,0 +1,471 @@
# arm cpu features
config BR2_ARM_CPU_HAS_NEON
bool
# for some cores, NEON support is optional
config BR2_ARM_CPU_MAYBE_HAS_NEON
bool
# for some cores, VFPv2 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV2
bool
config BR2_ARM_CPU_HAS_VFPV2
bool
# for some cores, VFPv3 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV3
bool
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
config BR2_ARM_CPU_HAS_VFPV3
bool
select BR2_ARM_CPU_HAS_VFPV2
# for some cores, VFPv4 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV4
bool
select BR2_ARM_CPU_MAYBE_HAS_VFPV3
config BR2_ARM_CPU_HAS_VFPV4
bool
select BR2_ARM_CPU_HAS_VFPV3
config BR2_ARM_CPU_HAS_ARM
bool
config BR2_ARM_CPU_HAS_THUMB
bool
config BR2_ARM_CPU_HAS_THUMB2
bool
config BR2_ARM_CPU_ARMV4
bool
config BR2_ARM_CPU_ARMV5
bool
config BR2_ARM_CPU_ARMV6
bool
config BR2_ARM_CPU_ARMV7A
bool
choice
prompt "Target Architecture Variant"
depends on BR2_arm || BR2_armeb
default BR2_arm926t
help
Specific CPU variant to use
config BR2_arm920t
bool "arm920t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm922t
bool "arm922t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm926t
bool "arm926t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1136j_s
bool "arm1136j-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1136jf_s
bool "arm1136jf-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1176jz_s
bool "arm1176jz-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1176jzf_s
bool "arm1176jzf-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm11mpcore
bool "mpcore"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_VFPV2
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a5
bool "cortex-A5"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a7
bool "cortex-A7"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a8
bool "cortex-A8"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a9
bool "cortex-A9"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a12
bool "cortex-A12"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a15
bool "cortex-A15"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_m3
bool "cortex-M3"
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_HAS_THUMB2
config BR2_fa526
bool "fa526/626"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_pj4
bool "pj4"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_strongarm
bool "strongarm sa110/sa1100"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_xscale
bool "xscale"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_iwmmxt
bool "iwmmxt"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
endchoice
config BR2_ARM_ENABLE_NEON
bool "Enable NEON SIMD extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_HAS_NEON
help
For some CPU cores, the NEON SIMD extension is optional.
Select this option if you are certain your particular
implementation has NEON support and you want to use it.
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
help
For some CPU cores, the VFP extension is optional. Select
this option if you are certain your particular
implementation has VFP support and you want to use it.
choice
prompt "Target ABI"
depends on BR2_arm || BR2_armeb
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_EABI
help
Application Binary Interface to use. The Application Binary
Interface describes the calling conventions (how arguments
are passed to functions, how the return value is passed, how
system calls are made, etc.).
config BR2_ARM_EABI
bool "EABI"
help
The EABI is currently the standard ARM ABI, which is used in
most projects. It supports both the 'soft' floating point
model (in which floating point instructions are emulated in
software) and the 'softfp' floating point model (in which
floating point instructions are executed using an hardware
floating point unit, but floating point arguments to
functions are passed in integer registers).
The 'softfp' floating point model is link-compatible with
the 'soft' floating point model, i.e you can link a library
built 'soft' with some other code built 'softfp'.
However, passing the floating point arguments in integer
registers is a bit inefficient, so if your ARM processor has
a floating point unit, and you don't have pre-compiled
'soft' or 'softfp' code, using the EABIhf ABI will provide
better floating point performances.
If your processor does not have a floating point unit, then
you must use this ABI.
config BR2_ARM_EABIHF
bool "EABIhf"
depends on BR2_ARM_CPU_HAS_VFPV2
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
unit to execute floating point instructions, and passes
floating point arguments in floating point registers.
It is more efficient than EABI for floating point related
workload. However, it does not allow to link against code
that has been pre-built for the 'soft' or 'softfp' floating
point models.
If your processor has a floating point unit, and you don't
depend on existing pre-compiled code, this option is most
likely the best choice.
endchoice
choice
prompt "Floating point strategy"
depends on BR2_ARM_EABI || BR2_ARM_EABIHF
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
config BR2_ARM_SOFT_FLOAT
bool "Soft float"
depends on BR2_ARM_EABI
select BR2_SOFT_FLOAT
help
This option allows to use software emulated floating
point. It should be used for ARM cores that do not include a
Vector Floating Point unit, such as ARMv5 cores (ARM926 for
example) or certain ARMv6 cores.
config BR2_ARM_FPU_VFPV2
bool "VFPv2"
depends on BR2_ARM_CPU_HAS_VFPV2
help
This option allows to use the VFPv2 floating point unit, as
available in some ARMv5 processors (ARM926EJ-S) and some
ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
MPCore).
Note that this option is also safe to use for newer cores
such as Cortex-A, because the VFPv3 and VFPv4 units are
backward compatible with VFPv2.
config BR2_ARM_FPU_VFPV3
bool "VFPv3"
depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
option requires a VFPv3 unit that has 32 double-precision
registers, which is not necessarily the case in all SOCs
based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
instead, which is guaranteed to work on all Cortex-A{8, 9}.
Note that this option is also safe to use for newer cores
that have a VFPv4 unit, because VFPv4 is backward compatible
with VFPv3. They must of course also have 32
double-precision registers.
config BR2_ARM_FPU_VFPV3D16
bool "VFPv3-D16"
depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
option requires a VFPv3 unit that has 16 double-precision
registers, which is generally the case in all SOCs based on
Cortex-A{8, 9}, even though VFPv3 is technically optional on
Cortex-A9. This is the safest option for those cores.
Note that this option is also safe to use for newer cores
such that have a VFPv4 unit, because the VFPv4 is backward
compatible with VFPv3.
config BR2_ARM_FPU_VFPV4
bool "VFPv4"
depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
15}). This option requires a VFPv4 unit that has 32
double-precision registers, which is not necessarily the
case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
unsure, you should probably use VFPv4-D16 instead.
Note that if you want binary code that works on all ARMv7
cores, including the earlier Cortex-A{8, 9}, you should
instead select VFPv3.
config BR2_ARM_FPU_VFPV4D16
bool "VFPv4-D16"
depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
15}). This option requires a VFPv4 unit that has 16
double-precision registers, which is always available on
Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
Cortex-A7.
Note that if you want binary code that works on all ARMv7
cores, including the earlier Cortex-A{8, 9}, you should
instead select VFPv3-D16.
config BR2_ARM_FPU_NEON
bool "NEON"
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use the NEON SIMD unit, as available
in some ARMv7 processors, as a floating-point unit. It
should however be noted that using NEON for floating point
operations doesn't provide a complete compatibility with the
IEEE 754.
config BR2_ARM_FPU_NEON_VFPV4
bool "NEON/VFPv4"
depends on BR2_ARM_CPU_HAS_VFPV4
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use both the VFPv4 and the NEON SIMD
units for floating point operations. Note that some ARMv7
cores do not necessarily have VFPv4 and/or NEON support, for
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
endchoice
choice
prompt "ARM instruction set"
config BR2_ARM_INSTRUCTIONS_ARM
bool "ARM"
depends on BR2_ARM_CPU_HAS_ARM
help
This option instructs the compiler to generate regular ARM
instructions, that are all 32 bits wide.
config BR2_ARM_INSTRUCTIONS_THUMB
bool "Thumb"
depends on BR2_ARM_CPU_HAS_THUMB
# Thumb-1 and VFP are not compatible
depends on BR2_ARM_SOFT_FLOAT
help
This option instructions the compiler to generate Thumb
instructions, which allows to mix 16 bits instructions and
32 bits instructions. This generally provides a much smaller
compiled binary size.
comment "Thumb1 is not compatible with VFP"
depends on BR2_ARM_CPU_HAS_THUMB
depends on !BR2_ARM_SOFT_FLOAT
config BR2_ARM_INSTRUCTIONS_THUMB2
bool "Thumb2"
depends on BR2_ARM_CPU_HAS_THUMB2
help
This option instructions the compiler to generate Thumb2
instructions, which allows to mix 16 bits instructions and
32 bits instructions. This generally provides a much smaller
compiled binary size.
endchoice
config BR2_ARCH
default "arm" if BR2_arm
default "armeb" if BR2_armeb
config BR2_ENDIAN
default "LITTLE" if BR2_arm
default "BIG" if BR2_armeb
config BR2_GCC_TARGET_CPU
default "arm920t" if BR2_arm920t
default "arm922t" if BR2_arm922t
default "arm926ej-s" if BR2_arm926t
default "arm1136j-s" if BR2_arm1136j_s
default "arm1136jf-s" if BR2_arm1136jf_s
default "arm1176jz-s" if BR2_arm1176jz_s
default "arm1176jzf-s" if BR2_arm1176jzf_s
default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
default "mpcorenovfp" if BR2_arm11mpcore
default "cortex-a5" if BR2_cortex_a5
default "cortex-a7" if BR2_cortex_a7
default "cortex-a8" if BR2_cortex_a8
default "cortex-a9" if BR2_cortex_a9
default "cortex-a12" if BR2_cortex_a12
default "cortex-a15" if BR2_cortex_a15
default "cortex-m3" if BR2_cortex_m3
default "fa526" if BR2_fa526
default "marvell-pj4" if BR2_pj4
default "strongarm" if BR2_strongarm
default "xscale" if BR2_xscale
default "iwmmxt" if BR2_iwmmxt
config BR2_GCC_TARGET_ABI
default "aapcs-linux"
config BR2_GCC_TARGET_FPU
default "vfp" if BR2_ARM_FPU_VFPV2
default "vfpv3" if BR2_ARM_FPU_VFPV3
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
default "vfpv4" if BR2_ARM_FPU_VFPV4
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
config BR2_GCC_TARGET_FLOAT_ABI
default "soft" if BR2_ARM_SOFT_FLOAT
default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
config BR2_GCC_TARGET_MODE
default "arm" if BR2_ARM_INSTRUCTIONS_ARM
default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2

107
deprecated/firmware/buildroot/arch/Config.in.bfin Normal file
View File

@@ -0,0 +1,107 @@
choice
prompt "Target CPU"
depends on BR2_bfin
default BR2_bf609
help
Specify target CPU
config BR2_bf606
bool "bf606"
config BR2_bf607
bool "bf607"
config BR2_bf608
bool "bf608"
config BR2_bf609
bool "bf609"
config BR2_bf512
bool "bf512"
config BR2_bf514
bool "bf514"
config BR2_bf516
bool "bf516"
config BR2_bf518
bool "bf518"
config BR2_bf522
bool "bf522"
config BR2_bf523
bool "bf523"
config BR2_bf524
bool "bf524"
config BR2_bf525
bool "bf525"
config BR2_bf526
bool "bf526"
config BR2_bf527
bool "bf527"
config BR2_bf531
bool "bf531"
config BR2_bf532
bool "bf532"
config BR2_bf533
bool "bf533"
config BR2_bf534
bool "bf534"
config BR2_bf536
bool "bf536"
config BR2_bf537
bool "bf537"
config BR2_bf538
bool "bf538"
config BR2_bf539
bool "bf539"
config BR2_bf542
bool "bf542"
config BR2_bf544
bool "bf544"
config BR2_bf547
bool "bf547"
config BR2_bf548
bool "bf548"
config BR2_bf549
bool "bf549"
config BR2_bf561
bool "bf561"
endchoice
config BR2_ARCH
default "bfin"
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_CPU
default bf606 if BR2_bf606
default bf607 if BR2_bf607
default bf608 if BR2_bf608
default bf609 if BR2_bf609
default bf512 if BR2_bf512
default bf514 if BR2_bf514
default bf516 if BR2_bf516
default bf518 if BR2_bf518
default bf522 if BR2_bf522
default bf523 if BR2_bf523
default bf524 if BR2_bf524
default bf525 if BR2_bf525
default bf526 if BR2_bf526
default bf527 if BR2_bf527
default bf531 if BR2_bf531
default bf532 if BR2_bf532
default bf533 if BR2_bf533
default bf534 if BR2_bf534
default bf536 if BR2_bf536
default bf537 if BR2_bf537
default bf538 if BR2_bf538
default bf539 if BR2_bf539
default bf542 if BR2_bf542
default bf544 if BR2_bf544
default bf547 if BR2_bf547
default bf548 if BR2_bf548
default bf549 if BR2_bf549
default bf561 if BR2_bf561
config BR2_GCC_TARGET_CPU_REVISION
string "Target CPU revision"
help
Specify a target CPU revision, which will be appended to the
value of the -mcpu option. For example, if the selected CPU is
bf609, and then selected CPU revision is "0.0", then gcc will
receive the -mcpu=bf609-0.0 option.

13
deprecated/firmware/buildroot/arch/Config.in.m68k Normal file
View File

@@ -0,0 +1,13 @@
config BR2_ARCH
default "m68k" if BR2_m68k
config BR2_ENDIAN
default "BIG"
config BR2_GCC_TARGET_ARCH
default "68000" if BR2_m68k_68000
default "68010" if BR2_m68k_68010
default "68020" if BR2_m68k_68020
default "68030" if BR2_m68k_68030
default "68040" if BR2_m68k_68040
default "68060" if BR2_m68k_68060

11
deprecated/firmware/buildroot/arch/Config.in.microblaze Normal file
View File

@@ -0,0 +1,11 @@
config BR2_ARCH
default "microblazeel" if BR2_microblazeel
default "microblaze" if BR2_microblazebe
config BR2_ENDIAN
default "LITTLE" if BR2_microblazeel
default "BIG" if BR2_microblazebe
config BR2_microblaze
bool
default y if BR2_microblazeel || BR2_microblazebe

85
deprecated/firmware/buildroot/arch/Config.in.mips Normal file
View File

@@ -0,0 +1,85 @@
choice
prompt "Target Architecture Variant"
depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
default BR2_mips_32 if BR2_mips || BR2_mipsel
default BR2_mips_64 if BR2_mips64 || BR2_mips64el
help
Specific CPU variant to use
64bit cabable: 64, 64r2, 64r6
non-64bit capable: 32, 32r2, 32r6
config BR2_mips_32
bool "mips 32"
depends on !BR2_ARCH_IS_64
config BR2_mips_32r2
bool "mips 32r2"
depends on !BR2_ARCH_IS_64
config BR2_mips_32r6
bool "mips 32r6"
depends on !BR2_ARCH_IS_64
config BR2_mips_64
bool "mips 64"
depends on BR2_ARCH_IS_64
config BR2_mips_64r2
bool "mips 64r2"
depends on BR2_ARCH_IS_64
config BR2_mips_64r6
bool "mips 64r6"
depends on BR2_ARCH_IS_64
endchoice
choice
prompt "Target ABI"
depends on BR2_mips64 || BR2_mips64el
default BR2_MIPS_NABI32
help
Application Binary Interface to use
config BR2_MIPS_NABI32
bool "n32"
depends on BR2_ARCH_IS_64
select BR2_KERNEL_64_USERLAND_32
config BR2_MIPS_NABI64
bool "n64"
depends on BR2_ARCH_IS_64
endchoice
config BR2_MIPS_SOFT_FLOAT
bool "Use soft-float"
default y
select BR2_SOFT_FLOAT
help
If your target CPU does not have a Floating Point Unit (FPU)
or a kernel FPU emulator, but you still wish to support
floating point functions, then everything will need to be
compiled with soft floating point support (-msoft-float).
config BR2_ARCH
default "mips" if BR2_mips
default "mipsel" if BR2_mipsel
default "mips64" if BR2_mips64
default "mips64el" if BR2_mips64el
config BR2_ENDIAN
default "LITTLE" if BR2_mipsel || BR2_mips64el
default "BIG" if BR2_mips || BR2_mips64
config BR2_GCC_TARGET_ARCH
default "mips32" if BR2_mips_32
default "mips32r2" if BR2_mips_32r2
default "mips32r6" if BR2_mips_32r6
default "mips64" if BR2_mips_64
default "mips64r2" if BR2_mips_64r2
default "mips64r6" if BR2_mips_64r6
config BR2_MIPS_OABI32
bool
default y if BR2_mips || BR2_mipsel
config BR2_GCC_TARGET_ABI
default "32" if BR2_MIPS_OABI32
default "n32" if BR2_MIPS_NABI32
default "64" if BR2_MIPS_NABI64

5
deprecated/firmware/buildroot/arch/Config.in.nios2 Normal file
View File

@@ -0,0 +1,5 @@
config BR2_ARCH
default "nios2"
config BR2_ENDIAN
default "LITTLE"

214
deprecated/firmware/buildroot/arch/Config.in.powerpc Normal file
View File

@@ -0,0 +1,214 @@
config BR2_POWERPC_CPU_HAS_ALTIVEC
bool
config BR2_POWERPC_CPU_HAS_SPE
bool
choice
prompt "Target Architecture Variant"
default BR2_generic_powerpc
help
Specific CPU variant to use
config BR2_generic_powerpc
bool "generic"
config BR2_powerpc_401
bool "401"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_403
bool "403"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_405
bool "405"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_405fp
bool "405 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_440
bool "440"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_440fp
bool "440 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_464
bool "464"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_464fp
bool "464 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_476
bool "476"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_476fp
bool "476 with FPU"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_505
bool "505"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_601
bool "601"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_602
bool "602"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_603
bool "603"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_603e
bool "603e"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_604
bool "604"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_604e
bool "604e"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_620
bool "620"
config BR2_powerpc_630
bool "630"
config BR2_powerpc_740
bool "740"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_7400
bool "7400"
select BR2_POWERPC_CPU_HAS_ALTIVEC
depends on !BR2_ARCH_IS_64
config BR2_powerpc_7450
bool "7450"
select BR2_POWERPC_CPU_HAS_ALTIVEC
depends on !BR2_ARCH_IS_64
config BR2_powerpc_750
bool "750"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_821
bool "821"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_823
bool "823"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_860
bool "860"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_970
bool "970"
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_8540
bool "8540 / e500v1"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_8548
bool "8548 / e500v2"
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_e300c2
bool "e300c2"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e300c3
bool "e300c3"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e500mc
bool "e500mc"
depends on !BR2_ARCH_IS_64
config BR2_powerpc_e5500
bool "e5500"
depends on !BR2_powerpc64le
config BR2_powerpc_e6500
bool "e6500"
depends on !BR2_powerpc64le
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_power4
bool "power4"
config BR2_powerpc_power5
bool "power5"
config BR2_powerpc_power6
bool "power6"
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_power7
bool "power7"
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_power8
bool "power8"
select BR2_POWERPC_CPU_HAS_ALTIVEC
endchoice
choice
prompt "Target ABI"
default BR2_powerpc_SPE if BR2_POWERPC_CPU_HAS_SPE
default BR2_powerpc_CLASSIC
help
Application Binary Interface to use
config BR2_powerpc_CLASSIC
bool "Classic"
depends on !BR2_POWERPC_CPU_HAS_SPE
config BR2_powerpc_SPE
bool "SPE"
depends on BR2_POWERPC_CPU_HAS_SPE
endchoice
config BR2_POWERPC_SOFT_FLOAT
bool "Use soft-float"
select BR2_SOFT_FLOAT
help
If your target CPU does not have a Floating Point Unit (FPU)
or a kernel FPU emulator, but you still wish to support
floating point functions, then everything will need to be
compiled with soft floating point support (-msoft-float).
config BR2_ARCH
default "powerpc" if BR2_powerpc
default "powerpc64" if BR2_powerpc64
default "powerpc64le" if BR2_powerpc64le
config BR2_ENDIAN
default "BIG" if BR2_powerpc || BR2_powerpc64
default "LITTLE" if BR2_powerpc64le
config BR2_GCC_TARGET_CPU
default "401" if BR2_powerpc_401
default "403" if BR2_powerpc_403
default "405" if BR2_powerpc_405
default "405fp" if BR2_powerpc_405fp
default "440" if BR2_powerpc_440
default "440fp" if BR2_powerpc_440fp
default "464" if BR2_powerpc_464
default "464fp" if BR2_powerpc_464fp
default "476" if BR2_powerpc_476
default "476fp" if BR2_powerpc_476fp
default "505" if BR2_powerpc_505
default "601" if BR2_powerpc_601
default "602" if BR2_powerpc_602
default "603" if BR2_powerpc_603
default "603e" if BR2_powerpc_603e
default "604" if BR2_powerpc_604
default "604e" if BR2_powerpc_604e
default "620" if BR2_powerpc_620
default "630" if BR2_powerpc_630
default "740" if BR2_powerpc_740
default "7400" if BR2_powerpc_7400
default "7450" if BR2_powerpc_7450
default "750" if BR2_powerpc_750
default "821" if BR2_powerpc_821
default "823" if BR2_powerpc_823
default "860" if BR2_powerpc_860
default "970" if BR2_powerpc_970
default "8540" if BR2_powerpc_8540
default "8548" if BR2_powerpc_8548
default "e300c2" if BR2_powerpc_e300c2
default "e300c3" if BR2_powerpc_e300c3
default "e500mc" if BR2_powerpc_e500mc
default "e5500" if BR2_powerpc_e5500
default "e6500" if BR2_powerpc_e6500
default "power4" if BR2_powerpc_power4
default "power5" if BR2_powerpc_power5
default "power6" if BR2_powerpc_power6
default "power7" if BR2_powerpc_power7
default "power8" if BR2_powerpc_power8
config BR2_GCC_TARGET_ABI
default "altivec" if BR2_PPC_ABI_altivec
default "no-altivec" if BR2_PPC_ABI_no-altivec
default "spe" if BR2_PPC_ABI_spe
default "no-spe" if BR2_PPC_ABI_no-spe
default "ibmlongdouble" if BR2_PPC_ABI_ibmlongdouble
default "ieeelongdouble" if BR2_PPC_ABI_ieeelongdouble

30
deprecated/firmware/buildroot/arch/Config.in.sh Normal file
View File

@@ -0,0 +1,30 @@
choice
prompt "Target Architecture Variant"
depends on BR2_sh
default BR2_sh4
help
Specific CPU variant to use
config BR2_sh2a
bool "sh2a (SH2A big endian)"
config BR2_sh4
bool "sh4 (SH4 little endian)"
config BR2_sh4eb
bool "sh4eb (SH4 big endian)"
config BR2_sh4a
bool "sh4a (SH4A little endian)"
config BR2_sh4aeb
bool "sh4aeb (SH4A big endian)"
endchoice
config BR2_ARCH
default "sh2a" if BR2_sh2a
default "sh4" if BR2_sh4
default "sh4eb" if BR2_sh4eb
default "sh4a" if BR2_sh4a
default "sh4aeb" if BR2_sh4aeb
default "sh64" if BR2_sh64
config BR2_ENDIAN
default "LITTLE" if BR2_sh4 || BR2_sh4a || BR2_sh64
default "BIG" if BR2_sh2a || BR2_sh4eb || BR2_sh4aeb

30
deprecated/firmware/buildroot/arch/Config.in.sparc Normal file
View File

@@ -0,0 +1,30 @@
choice
prompt "Target Architecture Variant"
depends on BR2_sparc || BR2_sparc64
default BR2_sparc_v8 if BR2_sparc
default BR2_sparc_v9 if BR2_sparc64
help
Specific CPU variant to use
config BR2_sparc_v8
bool "v8"
depends on BR2_sparc
config BR2_sparc_leon3
bool "leon3"
depends on BR2_sparc
config BR2_sparc_v9
bool "v9"
depends on BR2_sparc64
endchoice
config BR2_ARCH
default "sparc" if BR2_sparc
default "sparc64" if BR2_sparc64
config BR2_ENDIAN
default "BIG"
config BR2_GCC_TARGET_CPU
default "leon3" if BR2_sparc_leon3
default "v8" if BR2_sparc_v8
default "ultrasparc" if BR2_sparc_v9

280
deprecated/firmware/buildroot/arch/Config.in.x86 Normal file
View File

@@ -0,0 +1,280 @@
# i386/x86_64 cpu features
config BR2_X86_CPU_HAS_MMX
bool
config BR2_X86_CPU_HAS_SSE
bool
config BR2_X86_CPU_HAS_SSE2
bool
config BR2_X86_CPU_HAS_SSE3
bool
config BR2_X86_CPU_HAS_SSSE3
bool
config BR2_X86_CPU_HAS_SSE4
bool
config BR2_X86_CPU_HAS_SSE42
bool
config BR2_X86_CPU_HAS_AVX
bool
config BR2_X86_CPU_HAS_AVX2
bool
choice
prompt "Target Architecture Variant"
depends on BR2_i386 || BR2_x86_64
default BR2_x86_i586 if BR2_i386
help
Specific CPU variant to use
config BR2_x86_i386
bool "i386"
depends on !BR2_x86_64
config BR2_x86_i486
bool "i486"
depends on !BR2_x86_64
config BR2_x86_i586
bool "i586"
depends on !BR2_x86_64
config BR2_x86_x1000
bool "x1000"
depends on !BR2_x86_64
help
The Intel X1000 is a Pentium class microprocessor in the
Quark (sub-Atom) Product Line. The X1000 has a bug on the
lock prefix requiring that prefix must be stripped at build
time.
See https://en.wikipedia.org/wiki/Intel_Quark
config BR2_x86_i686
bool "i686"
depends on !BR2_x86_64
config BR2_x86_pentiumpro
bool "pentium pro"
depends on !BR2_x86_64
config BR2_x86_pentium_mmx
bool "pentium MMX"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_pentium_m
bool "pentium mobile"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_pentium2
bool "pentium2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_pentium3
bool "pentium3"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_pentium4
bool "pentium4"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
depends on !BR2_x86_64
config BR2_x86_prescott
bool "prescott"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
depends on !BR2_x86_64
config BR2_x86_nocona
bool "nocona"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_core2
bool "core2"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
config BR2_x86_corei7
bool "corei7"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_corei7_avx
bool "corei7-avx"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
config BR2_x86_core_avx2
bool "core-avx2"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
select BR2_X86_CPU_HAS_AVX
select BR2_X86_CPU_HAS_AVX2
config BR2_x86_atom
bool "atom"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
config BR2_x86_k6
bool "k6"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_k6_2
bool "k6-2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_athlon
bool "athlon"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_athlon_4
bool "athlon-4"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_opteron
bool "opteron"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
config BR2_x86_opteron_sse3
bool "opteron w/ SSE3"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_barcelona
bool "barcelona"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
config BR2_x86_jaguar
bool "jaguar"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_steamroller
bool "steamroller"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_geode
bool "geode"
# Don't include MMX support because there several variant of geode
# processor, some with MMX support, some without.
# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
depends on !BR2_x86_64
config BR2_x86_c3
bool "Via/Cyrix C3 (Samuel/Ezra cores)"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_c32
bool "Via C3-2 (Nehemiah cores)"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_winchip_c6
bool "IDT Winchip C6"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
config BR2_x86_winchip2
bool "IDT Winchip 2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
endchoice
config BR2_ARCH
default "i386" if BR2_x86_i386
default "i486" if BR2_x86_i486
default "i586" if BR2_x86_i586
default "i586" if BR2_x86_x1000
default "i586" if BR2_x86_pentium_mmx
default "i586" if BR2_x86_geode
default "i586" if BR2_x86_c3
default "i686" if BR2_x86_c32
default "i586" if BR2_x86_winchip_c6
default "i586" if BR2_x86_winchip2
default "i686" if BR2_x86_i686
default "i686" if BR2_x86_pentium2
default "i686" if BR2_x86_pentium3
default "i686" if BR2_x86_pentium4
default "i686" if BR2_x86_pentium_m
default "i686" if BR2_x86_pentiumpro
default "i686" if BR2_x86_prescott
default "i686" if BR2_x86_nocona && BR2_i386
default "i686" if BR2_x86_core2 && BR2_i386
default "i686" if BR2_x86_corei7 && BR2_i386
default "i686" if BR2_x86_atom && BR2_i386
default "i686" if BR2_x86_opteron && BR2_i386
default "i686" if BR2_x86_opteron_sse3 && BR2_i386
default "i686" if BR2_x86_barcelona && BR2_i386
default "i686" if BR2_x86_jaguar && BR2_i386
default "i686" if BR2_x86_steamroller && BR2_i386
default "i686" if BR2_x86_k6
default "i686" if BR2_x86_k6_2
default "i686" if BR2_x86_athlon
default "i686" if BR2_x86_athlon_4
default "x86_64" if BR2_x86_64
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ARCH
default "i386" if BR2_x86_i386
default "i486" if BR2_x86_i486
default "i586" if BR2_x86_i586
default "i586" if BR2_x86_x1000
default "pentium-mmx" if BR2_x86_pentium_mmx
default "i686" if BR2_x86_i686
default "pentiumpro" if BR2_x86_pentiumpro
default "pentium-m" if BR2_x86_pentium_m
default "pentium2" if BR2_x86_pentium2
default "pentium3" if BR2_x86_pentium3
default "pentium4" if BR2_x86_pentium4
default "prescott" if BR2_x86_prescott
default "nocona" if BR2_x86_nocona
default "core2" if BR2_x86_core2
default "corei7" if BR2_x86_corei7
default "corei7-avx" if BR2_x86_corei7_avx
default "core-avx2" if BR2_x86_core_avx2
default "atom" if BR2_x86_atom
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
default "btver2" if BR2_x86_jaguar
default "bdver3" if BR2_x86_steamroller
default "k6" if BR2_x86_k6
default "k6-2" if BR2_x86_k6_2
default "athlon" if BR2_x86_athlon
default "athlon-4" if BR2_x86_athlon_4
default "winchip-c6" if BR2_x86_winchip_c6
default "winchip2" if BR2_x86_winchip2
default "c3" if BR2_x86_c3
default "c3-2" if BR2_x86_c32
default "geode" if BR2_x86_geode

56
deprecated/firmware/buildroot/arch/Config.in.xtensa Normal file
View File

@@ -0,0 +1,56 @@
choice
prompt "Target Architecture Variant"
depends on BR2_xtensa
default BR2_xtensa_fsf
config BR2_XTENSA_CUSTOM
select BR2_ARCH_HAS_MMU_OPTIONAL
bool "Custom Xtensa processor configuration"
config BR2_xtensa_fsf
select BR2_ARCH_HAS_MMU_MANDATORY
bool "fsf - Default configuration"
endchoice
config BR2_XTENSA_CUSTOM_NAME
string "Custom Xtensa processor configuration name"
depends on BR2_XTENSA_CUSTOM
default ""
help
Name given to a custom Xtensa processor configuration.
config BR2_XTENSA_CORE_NAME
string
default BR2_XTENSA_CUSTOM_NAME if BR2_XTENSA_CUSTOM
default "" if BR2_xtensa_fsf
config BR2_XTENSA_OVERLAY_DIR
string "Overlay directory for custom configuration"
depends on BR2_XTENSA_CUSTOM
default ""
help
Provide the directory path that contains the overlay file
for a custom processor configuration. The path is relative
to the top directory of buildroot.
These overlay files are tar packages with updated configuration
files for various toolchain packages and Xtensa processor
configurations. They are provided by the processor vendor or
directly from Tensilica.
choice
prompt "Target Architecture Endianness"
depends on BR2_XTENSA_CUSTOM
default BR2_XTENSA_LITTLE_ENDIAN
config BR2_XTENSA_LITTLE_ENDIAN
bool "Little endian"
config BR2_XTENSA_BIG_ENDIAN
bool "Big endian"
endchoice
config BR2_ENDIAN
default "LITTLE" if BR2_XTENSA_LITTLE_ENDIAN
default "BIG" if BR2_xtensa_fsf || BR2_XTENSA_BIG_ENDIAN
config BR2_ARCH
default "xtensa" if BR2_xtensa