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Bump buildroot to 2019.02

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This commit is contained in:
NADAL Jean-Baptiste
2019-03-28 22:49:48 +01:00
parent 5598b1b762
commit 920d307141
5121 changed files with 78550 additions and 46132 deletions
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147
bsp/buildroot/arch/Config.in
View File

@@ -15,9 +15,6 @@ config BR2_ARCH_HAS_MMU_MANDATORY
config BR2_ARCH_HAS_MMU_OPTIONAL
bool
config BR2_ARCH_HAS_FDPIC_SUPPORT
bool
choice
prompt "Target Architecture"
default BR2_i386
@@ -28,24 +25,25 @@ config BR2_arcle
bool "ARC (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
that can be used from deeply embedded to high performance host
applications. Little endian.
Synopsys' DesignWare ARC Processor Cores are a family of
32-bit CPUs that can be used from deeply embedded to high
performance host applications. Little endian.
config BR2_arceb
bool "ARC (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
that can be used from deeply embedded to high performance host
applications. Big endian.
Synopsys' DesignWare ARC Processor Cores are a family of
32-bit CPUs that can be used from deeply embedded to high
performance host applications. Big endian.
config BR2_arm
bool "ARM (little endian)"
# MMU support is set by the subarchitecture file, arch/Config.in.arm
help
ARM is a 32-bit reduced instruction set computer (RISC) instruction
set architecture (ISA) developed by ARM Holdings. Little endian.
ARM is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by ARM Holdings.
Little endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
@@ -53,8 +51,9 @@ config BR2_armeb
bool "ARM (big endian)"
# MMU support is set by the subarchitecture file, arch/Config.in.arm
help
ARM is a 32-bit reduced instruction set computer (RISC) instruction
set architecture (ISA) developed by ARM Holdings. Big endian.
ARM is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by ARM Holdings.
Big endian.
http://www.arm.com/
http://en.wikipedia.org/wiki/ARM
@@ -76,16 +75,6 @@ config BR2_aarch64_be
http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
http://en.wikipedia.org/wiki/ARM
config BR2_bfin
bool "Blackfin"
select BR2_ARCH_HAS_FDPIC_SUPPORT
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
help
The Blackfin is a family of 16 or 32-bit microprocessors developed,
manufactured and marketed by Analog Devices.
http://www.analog.com/
http://en.wikipedia.org/wiki/Blackfin
config BR2_csky
bool "csky"
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
@@ -113,8 +102,8 @@ config BR2_microblazeel
bool "Microblaze AXI (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
based architecture (little endian)
Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
bus based architecture (little endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
@@ -122,8 +111,8 @@ config BR2_microblazebe
bool "Microblaze non-AXI (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
based architecture (non-AXI, big endian)
Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
bus based architecture (non-AXI, big endian)
http://www.xilinx.com
http://en.wikipedia.org/wiki/Microblaze
@@ -131,7 +120,8 @@ config BR2_mips
bool "MIPS (big endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
MIPS is a RISC microprocessor from MIPS Technologies. Big
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
@@ -139,7 +129,8 @@ config BR2_mipsel
bool "MIPS (little endian)"
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
MIPS is a RISC microprocessor from MIPS Technologies. Little
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
@@ -148,7 +139,8 @@ config BR2_mips64
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
MIPS is a RISC microprocessor from MIPS Technologies. Big
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
@@ -157,7 +149,8 @@ config BR2_mips64el
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
MIPS is a RISC microprocessor from MIPS Technologies. Little
endian.
http://www.mips.com/
http://en.wikipedia.org/wiki/MIPS_Technologies
@@ -180,8 +173,8 @@ config BR2_powerpc
bool "PowerPC"
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Big endian.
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
@@ -190,8 +183,8 @@ config BR2_powerpc64
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Big endian.
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Big endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
@@ -200,17 +193,29 @@ config BR2_powerpc64le
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
Little endian.
PowerPC is a RISC architecture created by Apple-IBM-Motorola
alliance. Little endian.
http://www.power.org/
http://en.wikipedia.org/wiki/Powerpc
config BR2_riscv
bool "RISCV"
select BR2_ARCH_HAS_MMU_MANDATORY
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
help
RISC-V is an open, free Instruction Set Architecture created
by the UC Berkeley Architecture Research group and supported
and promoted by RISC-V Foundation.
https://riscv.org/
https://en.wikipedia.org/wiki/RISC-V
config BR2_sh
bool "SuperH"
select BR2_ARCH_HAS_MMU_OPTIONAL
help
SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
instruction set architecture (ISA) developed by Hitachi.
SuperH (or SH) is a 32-bit reduced instruction set computer
(RISC) instruction set architecture (ISA) developed by
Hitachi.
http://www.hitachi.com/
http://en.wikipedia.org/wiki/SuperH
@@ -218,8 +223,9 @@ config BR2_sparc
bool "SPARC"
select BR2_ARCH_HAS_MMU_MANDATORY
help
SPARC (from Scalable Processor Architecture) is a RISC instruction
set architecture (ISA) developed by Sun Microsystems.
SPARC (from Scalable Processor Architecture) is a RISC
instruction set architecture (ISA) developed by Sun
Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
@@ -228,8 +234,9 @@ config BR2_sparc64
select BR2_ARCH_IS_64
select BR2_ARCH_HAS_MMU_MANDATORY
help
SPARC (from Scalable Processor Architecture) is a RISC instruction
set architecture (ISA) developed by Sun Microsystems.
SPARC (from Scalable Processor Architecture) is a RISC
instruction set architecture (ISA) developed by Sun
Microsystems.
http://www.oracle.com/sun
http://en.wikipedia.org/wiki/Sparc
@@ -283,6 +290,10 @@ config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
# The following string values are defined by the individual
# Config.in.$ARCH files
config BR2_ARCH
@@ -306,9 +317,6 @@ config BR2_GCC_TARGET_FP32_MODE
config BR2_GCC_TARGET_CPU
string
config BR2_GCC_TARGET_CPU_REVISION
string
# The value of this option will be passed as --with-fpu=<value> when
# building gcc (internal backend) or -mfpu=<value> in the toolchain
# wrapper (external toolchain)
@@ -341,7 +349,6 @@ config BR2_READELF_ARCH_NAME
choice
prompt "Target Binary Format"
default BR2_BINFMT_ELF if BR2_USE_MMU
default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
default BR2_BINFMT_FLAT
config BR2_BINFMT_ELF
@@ -349,56 +356,34 @@ config BR2_BINFMT_ELF
depends on BR2_USE_MMU
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF (Executable and Linkable Format) is a format for libraries and
executables used across different architectures and operating
systems.
config BR2_BINFMT_FDPIC
bool "FDPIC"
depends on BR2_ARCH_HAS_FDPIC_SUPPORT
select BR2_BINFMT_SUPPORTS_SHARED
help
ELF FDPIC binaries are based on ELF, but allow the individual load
segments of a binary to be located in memory independently of each
other. This makes this format ideal for use in environments where no
MMU is available.
ELF (Executable and Linkable Format) is a format for libraries
and executables used across different architectures and
operating systems.
config BR2_BINFMT_FLAT
bool "FLAT"
depends on !BR2_USE_MMU
help
FLAT binary is a relatively simple and lightweight executable format
based on the original a.out format. It is widely used in environment
where no MMU is available.
FLAT binary is a relatively simple and lightweight executable
format based on the original a.out format. It is widely used
in environment where no MMU is available.
endchoice
# Set up flat binary type
choice
prompt "FLAT Binary type"
depends on BR2_BINFMT_FLAT
default BR2_BINFMT_FLAT_ONE
depends on BR2_BINFMT_FLAT
config BR2_BINFMT_FLAT_ONE
bool "One memory region"
help
All segments are linked into one memory region.
config BR2_BINFMT_FLAT_SEP_DATA
bool "Separate data and code region"
# this FLAT binary type technically exists on m68k, but fails
# to build numerous packages: due to architecture limitation,
# big functions cannot be built in this mode. They cause build
# failures such as "Tried to convert PC relative branch to
# absolute jump" or "error: value -yyyyy out of range".
depends on BR2_bfin
help
Allow for the data and text segments to be separated and placed in
different regions of memory.
config BR2_BINFMT_FLAT_SHARED
bool "Shared binary"
depends on BR2_m68k || BR2_bfin
depends on BR2_m68k
# Even though this really generates shared binaries, there is no libdl
# and dlopen() cannot be used. So packages that require shared
# libraries cannot be built. Therefore, we don't select
@@ -418,10 +403,6 @@ if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
source "arch/Config.in.arm"
endif
if BR2_bfin
source "arch/Config.in.bfin"
endif
if BR2_csky
source "arch/Config.in.csky"
endif
@@ -450,6 +431,10 @@ if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
source "arch/Config.in.powerpc"
endif
if BR2_riscv
source "arch/Config.in.riscv"
endif
if BR2_sh
source "arch/Config.in.sh"
endif

2
bsp/buildroot/arch/Config.in.arc
View File

@@ -1,7 +1,7 @@
choice
prompt "Target CPU"
depends on BR2_arc
default BR2_arc770d
depends on BR2_arc
help
Specific CPU to use

141
bsp/buildroot/arch/Config.in.arm
View File

@@ -6,12 +6,21 @@ config BR2_ARM_CPU_HAS_NEON
config BR2_ARM_CPU_MAYBE_HAS_NEON
bool
# For some cores, the FPU is optional
config BR2_ARM_CPU_MAYBE_HAS_FPU
bool
config BR2_ARM_CPU_HAS_FPU
bool
# for some cores, VFPv2 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV2
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_VFPV2
bool
select BR2_ARM_CPU_HAS_FPU
# for some cores, VFPv3 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV3
@@ -31,6 +40,24 @@ config BR2_ARM_CPU_HAS_VFPV4
bool
select BR2_ARM_CPU_HAS_VFPV3
# FPv4 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV4
bool
select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_FPV4
bool
select BR2_ARM_CPU_HAS_FPU
# FPv5 is always optional
config BR2_ARM_CPU_MAYBE_HAS_FPV5
bool
select BR2_ARM_CPU_MAYBE_HAS_FPV4
config BR2_ARM_CPU_HAS_FPV5
bool
select BR2_ARM_CPU_HAS_FPV4
config BR2_ARM_CPU_HAS_FP_ARMV8
bool
select BR2_ARM_CPU_HAS_VFPV4
@@ -240,7 +267,14 @@ config BR2_cortex_m3
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m7
bool "cortex-M7"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_ARMV7M
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
endif # !BR2_ARCH_IS_64
comment "armv8 cores"
@@ -342,25 +376,19 @@ config BR2_exynos_m1
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
if BR2_ARCH_IS_64
config BR2_falkor
bool "falkor"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_qdf24xx
bool "qdf24xx"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
if BR2_ARCH_IS_64
config BR2_thunderx
bool "thunderx"
select BR2_ARM_CPU_HAS_FP_ARMV8
@@ -406,32 +434,55 @@ if BR2_ARCH_IS_64
comment "armv8.1a cores"
config BR2_thunderx2t99
bool "thunderx2t99"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderx2t99p1
bool "thunderx2t99p1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_vulcan
bool "vulcan"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
endif # BR2_ARCH_IS_64
if BR2_ARCH_IS_64
comment "armv8.2a cores"
config BR2_cortex_a55
bool "cortex-A55"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_cortex_a75
bool "cortex-A75"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
config BR2_cortex_a75_a55
bool "cortex-A75/A55 big.LITTLE"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
endif # BR2_ARCH_IS_64
if BR2_ARCH_IS_64
comment "armv8.3a cores"
config BR2_saphira
bool "saphira"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
endif # BR2_ARCH_IS_64
endchoice
config BR2_ARM_ENABLE_NEON
@@ -445,7 +496,9 @@ config BR2_ARM_ENABLE_NEON
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
@@ -456,9 +509,9 @@ config BR2_ARM_ENABLE_VFP
choice
prompt "Target ABI"
depends on BR2_arm || BR2_armeb
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
default BR2_ARM_EABI
depends on BR2_arm || BR2_armeb
help
Application Binary Interface to use. The Application Binary
Interface describes the calling conventions (how arguments
@@ -491,7 +544,7 @@ config BR2_ARM_EABI
config BR2_ARM_EABIHF
bool "EABIhf"
depends on BR2_ARM_CPU_HAS_VFPV2
depends on BR2_ARM_CPU_HAS_FPU
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
@@ -512,10 +565,12 @@ endchoice
choice
prompt "Floating point strategy"
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
config BR2_ARM_SOFT_FLOAT
bool "Soft float"
@@ -622,6 +677,38 @@ config BR2_ARM_FPU_NEON_VFPV4
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
config BR2_ARM_FPU_FPV4D16
bool "FPv4-D16"
depends on BR2_ARM_CPU_HAS_FPV4
help
This option allows to use the FPv4-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M4).
config BR2_ARM_FPU_FPV5D16
bool "FPv5-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-SP (single precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FPV5DPD16
bool "FPv5-DP-D16"
depends on BR2_ARM_CPU_HAS_FPV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
help
This option allows to use the FPv5-DP (double precision)
floating point unit, as available in some ARMv7m processors
(Cortex-M7).
Note that if you want binary code that works on the earlier
Cortex-M4, you should instead select FPv4-D16.
config BR2_ARM_FPU_FP_ARMV8
bool "FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
@@ -716,6 +803,7 @@ config BR2_GCC_TARGET_CPU
# armv7m
default "cortex-m3" if BR2_cortex_m3
default "cortex-m4" if BR2_cortex_m4
default "cortex-m7" if BR2_cortex_m7
# armv8a
default "cortex-a32" if BR2_cortex_a32
default "cortex-a35" if BR2_cortex_a35
@@ -740,13 +828,18 @@ config BR2_GCC_TARGET_CPU
default "thunderx2t99" if BR2_thunderx2t99
default "thunderx2t99p1" if BR2_thunderx2t99p1
default "vulcan" if BR2_vulcan
# armv8.2a
default "cortex-a55" if BR2_cortex_a55
default "cortex-a75" if BR2_cortex_a75
default "cortex-a75.cortex-a55" if BR2_cortex_a75_a55
# armv8.3a
default "saphira" if BR2_saphira
config BR2_GCC_TARGET_ABI
default "aapcs-linux" if BR2_arm || BR2_armeb
default "lp64" if BR2_aarch64 || BR2_aarch64_be
config BR2_GCC_TARGET_FPU
depends on BR2_arm || BR2_armeb
default "vfp" if BR2_ARM_FPU_VFPV2
default "vfpv3" if BR2_ARM_FPU_VFPV3
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
@@ -754,8 +847,12 @@ config BR2_GCC_TARGET_FPU
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
depends on BR2_arm || BR2_armeb
config BR2_GCC_TARGET_FLOAT_ABI
default "soft" if BR2_ARM_SOFT_FLOAT

102
bsp/buildroot/arch/Config.in.bfin
View File

@@ -1,102 +0,0 @@
choice
prompt "Target CPU"
depends on BR2_bfin
default BR2_bf532
help
Specify target CPU
config BR2_bf512
bool "bf512"
config BR2_bf514
bool "bf514"
config BR2_bf516
bool "bf516"
config BR2_bf518
bool "bf518"
config BR2_bf522
bool "bf522"
config BR2_bf523
bool "bf523"
config BR2_bf524
bool "bf524"
config BR2_bf525
bool "bf525"
config BR2_bf526
bool "bf526"
config BR2_bf527
bool "bf527"
config BR2_bf531
bool "bf531"
config BR2_bf532
bool "bf532"
config BR2_bf533
bool "bf533"
config BR2_bf534
bool "bf534"
config BR2_bf536
bool "bf536"
config BR2_bf537
bool "bf537"
config BR2_bf538
bool "bf538"
config BR2_bf539
bool "bf539"
config BR2_bf542
bool "bf542"
config BR2_bf544
bool "bf544"
config BR2_bf547
bool "bf547"
config BR2_bf548
bool "bf548"
config BR2_bf549
bool "bf549"
config BR2_bf561
bool "bf561"
endchoice
config BR2_ARCH
default "bfin"
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_CPU
default bf606 if BR2_bf606
default bf607 if BR2_bf607
default bf608 if BR2_bf608
default bf609 if BR2_bf609
default bf512 if BR2_bf512
default bf514 if BR2_bf514
default bf516 if BR2_bf516
default bf518 if BR2_bf518
default bf522 if BR2_bf522
default bf523 if BR2_bf523
default bf524 if BR2_bf524
default bf525 if BR2_bf525
default bf526 if BR2_bf526
default bf527 if BR2_bf527
default bf531 if BR2_bf531
default bf532 if BR2_bf532
default bf533 if BR2_bf533
default bf534 if BR2_bf534
default bf536 if BR2_bf536
default bf537 if BR2_bf537
default bf538 if BR2_bf538
default bf539 if BR2_bf539
default bf542 if BR2_bf542
default bf544 if BR2_bf544
default bf547 if BR2_bf547
default bf548 if BR2_bf548
default bf549 if BR2_bf549
default bf561 if BR2_bf561
config BR2_GCC_TARGET_CPU_REVISION
string "Target CPU revision"
help
Specify a target CPU revision, which will be appended to the
value of the -mcpu option. For example, if the selected CPU is
bf609, and then selected CPU revision is "0.0", then gcc will
receive the -mcpu=bf609-0.0 option.
config BR2_READELF_ARCH_NAME
default "Analog Devices Blackfin"

2
bsp/buildroot/arch/Config.in.m68k
View File

@@ -15,8 +15,8 @@ config BR2_m68k_cf
# coldfire variants will be added later
choice
prompt "Target CPU"
depends on BR2_m68k
default BR2_m68k_68040
depends on BR2_m68k
help
Specific CPU variant to use

50
bsp/buildroot/arch/Config.in.mips
View File

@@ -5,6 +5,9 @@ config BR2_MIPS_CPU_MIPS32
config BR2_MIPS_CPU_MIPS32R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R3
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
@@ -18,6 +21,9 @@ config BR2_MIPS_CPU_MIPS64
config BR2_MIPS_CPU_MIPS64R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R3
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
@@ -28,14 +34,14 @@ config BR2_MIPS_CPU_MIPS64R6
choice
prompt "Target Architecture Variant"
depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
default BR2_mips_32 if BR2_mips || BR2_mipsel
default BR2_mips_64 if BR2_mips64 || BR2_mips64el
depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
help
Specific CPU variant to use
64bit cabable: 64, 64r2, 64r5, 64r6
non-64bit capable: 32, 32r2, 32r5, 32r6
64bit capable: 64, 64r2, 64r3, 64r5, 64r6
non-64bit capable: 32, 32r2, 32r3, 32r5, 32r6
config BR2_mips_32
bool "Generic MIPS32"
@@ -45,6 +51,10 @@ config BR2_mips_32r2
bool "Generic MIPS32R2"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
config BR2_mips_32r3
bool "Generic MIPS32R3"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R3
config BR2_mips_32r5
bool "Generic MIPS32R5"
depends on !BR2_ARCH_IS_64
@@ -95,6 +105,10 @@ config BR2_mips_64r2
bool "Generic MIPS64R2"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R2
config BR2_mips_64r3
bool "Generic MIPS64R3"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R3
config BR2_mips_64r5
bool "Generic MIPS64R5"
depends on BR2_ARCH_IS_64
@@ -108,6 +122,20 @@ config BR2_mips_i6400
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R6
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_octeon2
bool "Octeon II"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R2
help
Marvell (formerly Cavium Networks) Octeon II CN60XX
processors.
config BR2_mips_octeon3
bool "Octeon III"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R3
help
Marvell (formerly Cavium Networks) Octeon III CN7XXX
processors.
config BR2_mips_p6600
bool "P6600"
depends on BR2_ARCH_IS_64
@@ -115,11 +143,10 @@ config BR2_mips_p6600
select BR2_MIPS_CPU_MIPS64R6
endchoice
choice
prompt "Target ABI"
depends on BR2_mips64 || BR2_mips64el
default BR2_MIPS_NABI32
depends on BR2_mips64 || BR2_mips64el
help
Application Binary Interface to use
@@ -136,6 +163,7 @@ endchoice
config BR2_MIPS_SOFT_FLOAT
bool "Use soft-float"
default y
depends on !BR2_mips_octeon3 # hard-float only
select BR2_SOFT_FLOAT
help
If your target CPU does not have a Floating Point Unit (FPU)
@@ -145,11 +173,11 @@ config BR2_MIPS_SOFT_FLOAT
choice
prompt "FP mode"
depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
default BR2_MIPS_FP32_MODE_XX
depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
help
MIPS32 supports different FP modes (32,xx,64). Information about FP
modes can be found here:
MIPS32 supports different FP modes (32,xx,64). Information
about FP modes can be found here:
https://sourceware.org/binutils/docs/as/MIPS-Options.html
https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
@@ -180,8 +208,8 @@ config BR2_MIPS_NAN_2008
choice
prompt "Target NaN"
depends on BR2_mips_32r5 || BR2_mips_64r5
default BR2_MIPS_ENABLE_NAN_2008
depends on BR2_mips_32r5 || BR2_mips_64r5
help
MIPS supports two different NaN encodings, legacy and 2008.
Information about MIPS NaN encodings can be found here:
@@ -214,6 +242,7 @@ config BR2_ENDIAN
config BR2_GCC_TARGET_ARCH
default "mips32" if BR2_mips_32
default "mips32r2" if BR2_mips_32r2
default "mips32r3" if BR2_mips_32r3
default "mips32r5" if BR2_mips_32r5
default "mips32r6" if BR2_mips_32r6
default "interaptiv" if BR2_mips_interaptiv
@@ -223,9 +252,12 @@ config BR2_GCC_TARGET_ARCH
default "mips32r2" if BR2_mips_xburst
default "mips64" if BR2_mips_64
default "mips64r2" if BR2_mips_64r2
default "mips64r3" if BR2_mips_64r3
default "mips64r5" if BR2_mips_64r5
default "mips64r6" if BR2_mips_64r6
default "i6400" if BR2_mips_i6400
default "octeon2" if BR2_mips_octeon2
default "octeon3" if BR2_mips_octeon3
default "p6600" if BR2_mips_p6600
config BR2_MIPS_OABI32

4
bsp/buildroot/arch/Config.in.powerpc
View File

@@ -71,12 +71,12 @@ config BR2_powerpc_740
depends on !BR2_ARCH_IS_64
config BR2_powerpc_7400
bool "7400"
select BR2_POWERPC_CPU_HAS_ALTIVEC
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_7450
bool "7450"
select BR2_POWERPC_CPU_HAS_ALTIVEC
depends on !BR2_ARCH_IS_64
select BR2_POWERPC_CPU_HAS_ALTIVEC
config BR2_powerpc_750
bool "750"
depends on !BR2_ARCH_IS_64

127
bsp/buildroot/arch/Config.in.riscv Normal file
View File

@@ -0,0 +1,127 @@
# RISC-V CPU ISA extensions.
config BR2_RISCV_ISA_RVI
bool
config BR2_RISCV_ISA_RVM
bool
config BR2_RISCV_ISA_RVA
bool
config BR2_RISCV_ISA_RVF
bool
config BR2_RISCV_ISA_RVD
bool
config BR2_RISCV_ISA_RVC
bool
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
config BR2_riscv_g
bool "General purpose (G)"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_RVM
select BR2_RISCV_ISA_RVA
select BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
help
General purpose (G) is equivalent to IMAFD.
config BR2_riscv_custom
bool "Custom architecture"
select BR2_RISCV_ISA_RVI
select BR2_RISCV_ISA_CUSTOM_RVA
endchoice
if BR2_riscv_custom
comment "Instruction Set Extensions"
config BR2_RISCV_ISA_CUSTOM_RVM
bool "Integer Multiplication and Division (M)"
select BR2_RISCV_ISA_RVM
config BR2_RISCV_ISA_CUSTOM_RVA
bool "Atomic Instructions (A)"
select BR2_RISCV_ISA_RVA
config BR2_RISCV_ISA_CUSTOM_RVF
bool "Single-precision Floating-point (F)"
select BR2_RISCV_ISA_RVF
config BR2_RISCV_ISA_CUSTOM_RVD
bool "Double-precision Floating-point (D)"
depends on BR2_RISCV_ISA_RVF
select BR2_RISCV_ISA_RVD
config BR2_RISCV_ISA_CUSTOM_RVC
bool "Compressed Instructions (C)"
select BR2_RISCV_ISA_RVC
endif
choice
prompt "Target Architecture Size"
default BR2_RISCV_64
config BR2_RISCV_32
bool "32-bit"
config BR2_RISCV_64
bool "64-bit"
select BR2_ARCH_IS_64
endchoice
choice
prompt "Target ABI"
default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64
default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64
config BR2_RISCV_ABI_ILP32
bool "ilp32"
depends on !BR2_ARCH_IS_64
config BR2_RISCV_ABI_ILP32F
bool "ilp32f"
depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
config BR2_RISCV_ABI_ILP32D
bool "ilp32d"
depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
config BR2_RISCV_ABI_LP64
bool "lp64"
depends on BR2_ARCH_IS_64
config BR2_RISCV_ABI_LP64F
bool "lp64f"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
config BR2_RISCV_ABI_LP64D
bool "lp64d"
depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
endchoice
config BR2_ARCH
default "riscv32" if !BR2_ARCH_IS_64
default "riscv64" if BR2_ARCH_IS_64
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_ABI
default "ilp32" if BR2_RISCV_ABI_ILP32
default "ilp32f" if BR2_RISCV_ABI_ILP32F
default "ilp32d" if BR2_RISCV_ABI_ILP32D
default "lp64" if BR2_RISCV_ABI_LP64
default "lp64f" if BR2_RISCV_ABI_LP64F
default "lp64d" if BR2_RISCV_ABI_LP64D
config BR2_READELF_ARCH_NAME
default "RISC-V"

2
bsp/buildroot/arch/Config.in.sh
View File

@@ -1,7 +1,7 @@
choice
prompt "Target Architecture Variant"
depends on BR2_sh
default BR2_sh4
depends on BR2_sh
help
Specific CPU variant to use

2
bsp/buildroot/arch/Config.in.sparc
View File

@@ -1,8 +1,8 @@
choice
prompt "Target Architecture Variant"
depends on BR2_sparc || BR2_sparc64
default BR2_sparc_v8 if BR2_sparc
default BR2_sparc_v9 if BR2_sparc64
depends on BR2_sparc || BR2_sparc64
help
Specific CPU variant to use

30
bsp/buildroot/arch/Config.in.x86
View File

@@ -20,8 +20,8 @@ config BR2_X86_CPU_HAS_AVX2
choice
prompt "Target Architecture Variant"
depends on BR2_i386 || BR2_x86_64
default BR2_x86_i586 if BR2_i386
depends on BR2_i386 || BR2_x86_64
help
Specific CPU variant to use
@@ -50,35 +50,35 @@ config BR2_x86_pentiumpro
depends on !BR2_x86_64
config BR2_x86_pentium_mmx
bool "pentium MMX"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_pentium_m
bool "pentium mobile"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_pentium2
bool "pentium2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_pentium3
bool "pentium3"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_pentium4
bool "pentium4"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
depends on !BR2_x86_64
config BR2_x86_prescott
bool "prescott"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
depends on !BR2_x86_64
config BR2_x86_nocona
bool "nocona"
select BR2_X86_CPU_HAS_MMX
@@ -140,21 +140,21 @@ config BR2_x86_silvermont
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_k6
bool "k6"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_k6_2
bool "k6-2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_athlon
bool "athlon"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_athlon_4
bool "athlon-4"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_opteron
bool "opteron"
select BR2_X86_CPU_HAS_MMX
@@ -198,21 +198,21 @@ config BR2_x86_geode
depends on !BR2_x86_64
config BR2_x86_c3
bool "Via/Cyrix C3 (Samuel/Ezra cores)"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_c32
bool "Via C3-2 (Nehemiah cores)"
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
depends on !BR2_x86_64
config BR2_x86_winchip_c6
bool "IDT Winchip C6"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
config BR2_x86_winchip2
bool "IDT Winchip 2"
select BR2_X86_CPU_HAS_MMX
depends on !BR2_x86_64
select BR2_X86_CPU_HAS_MMX
endchoice
config BR2_ARCH

20
bsp/buildroot/arch/Config.in.xtensa
View File

@@ -1,15 +1,15 @@
choice
prompt "Target Architecture Variant"
depends on BR2_xtensa
default BR2_xtensa_fsf
depends on BR2_xtensa
config BR2_XTENSA_CUSTOM
select BR2_ARCH_HAS_MMU_OPTIONAL
bool "Custom Xtensa processor configuration"
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_xtensa_fsf
select BR2_ARCH_HAS_MMU_MANDATORY
bool "fsf - Default configuration"
select BR2_ARCH_HAS_MMU_MANDATORY
endchoice
@@ -20,18 +20,18 @@ config BR2_XTENSA_OVERLAY_FILE
Enter the path to the overlay tarball for a custom processor
configuration.
These overlay files are tar packages with updated configuration
files for various toolchain packages and Xtensa processor
configurations. They are provided by the processor vendor or
directly from Tensilica.
These overlay files are tar packages with updated
configuration files for various toolchain packages and Xtensa
processor configurations. They are provided by the processor
vendor or directly from Tensilica.
The path can be either absolute, or relative to the top directory
of buildroot.
The path can be either absolute, or relative to the top
directory of buildroot.
choice
prompt "Target Architecture Endianness"
depends on BR2_XTENSA_CUSTOM
default BR2_XTENSA_LITTLE_ENDIAN
depends on BR2_XTENSA_CUSTOM
config BR2_XTENSA_LITTLE_ENDIAN
bool "Little endian"

22
bsp/buildroot/arch/arch.mk Normal file
View File

@@ -0,0 +1,22 @@
################################################################################
#
# Architecture-specific definitions
#
################################################################################
# Allow GCC target configuration settings to be optionally
# overwritten by architecture specific makefiles.
# Makefiles must use the GCC_TARGET_* variables below instead
# of the BR2_GCC_TARGET_* versions.
GCC_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
GCC_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
GCC_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
GCC_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE))
GCC_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU))
GCC_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
GCC_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
GCC_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
# Include any architecture specific makefiles.
-include $(sort $(wildcard arch/arch.mk.*))

30
bsp/buildroot/arch/arch.mk.riscv Normal file
View File

@@ -0,0 +1,30 @@
#
# Configure the GCC_TARGET_ARCH variable and append the
# appropriate RISC-V ISA extensions.
#
ifeq ($(BR2_riscv),y)
ifeq ($(BR2_RISCV_64),y)
GCC_TARGET_ARCH := rv64i
else
GCC_TARGET_ARCH := rv32i
endif
ifeq ($(BR2_RISCV_ISA_RVM),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
endif
ifeq ($(BR2_RISCV_ISA_RVA),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
endif
ifeq ($(BR2_RISCV_ISA_RVF),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
endif
ifeq ($(BR2_RISCV_ISA_RVD),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
endif
ifeq ($(BR2_RISCV_ISA_RVC),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
endif
endif

2
bsp/buildroot/arch/arch.mk.xtensa
View File

@@ -12,7 +12,7 @@
BR_ARCH_XTENSA_OVERLAY_FILE = $(call qstrip,$(BR2_XTENSA_OVERLAY_FILE))
ifneq ($(filter http://% https://% ftp://% scp://%,$(BR_ARCH_XTENSA_OVERLAY_FILE)),)
ARCH_XTENSA_OVERLAY_URL = $(BR_ARCH_XTENSA_OVERLAY_FILE)
ARCH_XTENSA_OVERLAY_FILE = $(DL_DIR)/$(notdir $(BR_ARCH_XTENSA_OVERLAY_FILE))
ARCH_XTENSA_OVERLAY_FILE = $($(PKG)_DL_DIR)/$(notdir $(BR_ARCH_XTENSA_OVERLAY_FILE))
# Do not check that file, we can't know its hash
BR_NO_CHECK_HASH_FOR += $(notdir $(ARCH_XTENSA_OVERLAY_URL))
else