Bump buildroot to 2019.02
This commit is contained in:
@@ -15,9 +15,6 @@ config BR2_ARCH_HAS_MMU_MANDATORY
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config BR2_ARCH_HAS_MMU_OPTIONAL
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bool
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config BR2_ARCH_HAS_FDPIC_SUPPORT
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bool
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choice
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prompt "Target Architecture"
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default BR2_i386
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@@ -28,24 +25,25 @@ config BR2_arcle
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bool "ARC (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
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that can be used from deeply embedded to high performance host
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applications. Little endian.
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Synopsys' DesignWare ARC Processor Cores are a family of
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32-bit CPUs that can be used from deeply embedded to high
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performance host applications. Little endian.
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config BR2_arceb
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bool "ARC (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
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that can be used from deeply embedded to high performance host
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applications. Big endian.
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Synopsys' DesignWare ARC Processor Cores are a family of
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32-bit CPUs that can be used from deeply embedded to high
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performance host applications. Big endian.
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config BR2_arm
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bool "ARM (little endian)"
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# MMU support is set by the subarchitecture file, arch/Config.in.arm
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Little endian.
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ARM is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by ARM Holdings.
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Little endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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@@ -53,8 +51,9 @@ config BR2_armeb
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bool "ARM (big endian)"
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# MMU support is set by the subarchitecture file, arch/Config.in.arm
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help
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ARM is a 32-bit reduced instruction set computer (RISC) instruction
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set architecture (ISA) developed by ARM Holdings. Big endian.
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ARM is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by ARM Holdings.
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Big endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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@@ -76,16 +75,6 @@ config BR2_aarch64_be
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http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
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http://en.wikipedia.org/wiki/ARM
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config BR2_bfin
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bool "Blackfin"
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select BR2_ARCH_HAS_FDPIC_SUPPORT
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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help
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The Blackfin is a family of 16 or 32-bit microprocessors developed,
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manufactured and marketed by Analog Devices.
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http://www.analog.com/
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http://en.wikipedia.org/wiki/Blackfin
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config BR2_csky
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bool "csky"
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select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
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@@ -113,8 +102,8 @@ config BR2_microblazeel
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bool "Microblaze AXI (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
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based architecture (little endian)
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Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
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bus based architecture (little endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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@@ -122,8 +111,8 @@ config BR2_microblazebe
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bool "Microblaze non-AXI (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
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based architecture (non-AXI, big endian)
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Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
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bus based architecture (non-AXI, big endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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@@ -131,7 +120,8 @@ config BR2_mips
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bool "MIPS (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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MIPS is a RISC microprocessor from MIPS Technologies. Big
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -139,7 +129,8 @@ config BR2_mipsel
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bool "MIPS (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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MIPS is a RISC microprocessor from MIPS Technologies. Little
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -148,7 +139,8 @@ config BR2_mips64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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MIPS is a RISC microprocessor from MIPS Technologies. Big
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -157,7 +149,8 @@ config BR2_mips64el
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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MIPS is a RISC microprocessor from MIPS Technologies. Little
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -180,8 +173,8 @@ config BR2_powerpc
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bool "PowerPC"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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Big endian.
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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@@ -190,8 +183,8 @@ config BR2_powerpc64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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Big endian.
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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@@ -200,17 +193,29 @@ config BR2_powerpc64le
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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Little endian.
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Little endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_riscv
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bool "RISCV"
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select BR2_ARCH_HAS_MMU_MANDATORY
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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help
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RISC-V is an open, free Instruction Set Architecture created
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by the UC Berkeley Architecture Research group and supported
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and promoted by RISC-V Foundation.
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https://riscv.org/
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https://en.wikipedia.org/wiki/RISC-V
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config BR2_sh
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bool "SuperH"
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select BR2_ARCH_HAS_MMU_OPTIONAL
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help
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SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by Hitachi.
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SuperH (or SH) is a 32-bit reduced instruction set computer
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(RISC) instruction set architecture (ISA) developed by
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Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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@@ -218,8 +223,9 @@ config BR2_sparc
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bool "SPARC"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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SPARC (from Scalable Processor Architecture) is a RISC instruction
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set architecture (ISA) developed by Sun Microsystems.
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SPARC (from Scalable Processor Architecture) is a RISC
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instruction set architecture (ISA) developed by Sun
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Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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@@ -228,8 +234,9 @@ config BR2_sparc64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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SPARC (from Scalable Processor Architecture) is a RISC instruction
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set architecture (ISA) developed by Sun Microsystems.
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SPARC (from Scalable Processor Architecture) is a RISC
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instruction set architecture (ISA) developed by Sun
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Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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@@ -283,6 +290,10 @@ config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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# The following string values are defined by the individual
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# Config.in.$ARCH files
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config BR2_ARCH
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@@ -306,9 +317,6 @@ config BR2_GCC_TARGET_FP32_MODE
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config BR2_GCC_TARGET_CPU
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string
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config BR2_GCC_TARGET_CPU_REVISION
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string
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# The value of this option will be passed as --with-fpu=<value> when
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# building gcc (internal backend) or -mfpu=<value> in the toolchain
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# wrapper (external toolchain)
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@@ -341,7 +349,6 @@ config BR2_READELF_ARCH_NAME
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choice
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prompt "Target Binary Format"
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default BR2_BINFMT_ELF if BR2_USE_MMU
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default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
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default BR2_BINFMT_FLAT
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config BR2_BINFMT_ELF
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@@ -349,56 +356,34 @@ config BR2_BINFMT_ELF
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depends on BR2_USE_MMU
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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ELF (Executable and Linkable Format) is a format for libraries and
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executables used across different architectures and operating
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systems.
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config BR2_BINFMT_FDPIC
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bool "FDPIC"
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depends on BR2_ARCH_HAS_FDPIC_SUPPORT
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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ELF FDPIC binaries are based on ELF, but allow the individual load
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segments of a binary to be located in memory independently of each
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other. This makes this format ideal for use in environments where no
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MMU is available.
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ELF (Executable and Linkable Format) is a format for libraries
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and executables used across different architectures and
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operating systems.
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config BR2_BINFMT_FLAT
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bool "FLAT"
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depends on !BR2_USE_MMU
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help
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FLAT binary is a relatively simple and lightweight executable format
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based on the original a.out format. It is widely used in environment
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where no MMU is available.
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FLAT binary is a relatively simple and lightweight executable
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format based on the original a.out format. It is widely used
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in environment where no MMU is available.
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endchoice
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# Set up flat binary type
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choice
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prompt "FLAT Binary type"
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depends on BR2_BINFMT_FLAT
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default BR2_BINFMT_FLAT_ONE
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depends on BR2_BINFMT_FLAT
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config BR2_BINFMT_FLAT_ONE
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bool "One memory region"
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help
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All segments are linked into one memory region.
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config BR2_BINFMT_FLAT_SEP_DATA
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bool "Separate data and code region"
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# this FLAT binary type technically exists on m68k, but fails
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# to build numerous packages: due to architecture limitation,
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# big functions cannot be built in this mode. They cause build
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# failures such as "Tried to convert PC relative branch to
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# absolute jump" or "error: value -yyyyy out of range".
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depends on BR2_bfin
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help
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Allow for the data and text segments to be separated and placed in
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different regions of memory.
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config BR2_BINFMT_FLAT_SHARED
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bool "Shared binary"
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depends on BR2_m68k || BR2_bfin
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depends on BR2_m68k
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# Even though this really generates shared binaries, there is no libdl
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# and dlopen() cannot be used. So packages that require shared
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# libraries cannot be built. Therefore, we don't select
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@@ -418,10 +403,6 @@ if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
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source "arch/Config.in.arm"
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endif
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if BR2_bfin
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source "arch/Config.in.bfin"
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endif
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if BR2_csky
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source "arch/Config.in.csky"
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endif
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@@ -450,6 +431,10 @@ if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
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source "arch/Config.in.powerpc"
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endif
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if BR2_riscv
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source "arch/Config.in.riscv"
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endif
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if BR2_sh
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source "arch/Config.in.sh"
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endif
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