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Bump buildroot to 2019.02

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This commit is contained in:
NADAL Jean-Baptiste
2019-03-28 22:49:48 +01:00
parent 5598b1b762
commit 920d307141
5121 changed files with 78550 additions and 46132 deletions
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52
bsp/buildroot/board/zynqmp/patches/uboot/0001-arm64-zynqmp-zcu106-fix-SPL-MMC-booting.patch Normal file
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@@ -0,0 +1,52 @@
From e5d72ed8339eb05285448aad3c89d21e4d18fd29 Mon Sep 17 00:00:00 2001
From: Luca Ceresoli <luca@lucaceresoli.net>
Date: Mon, 26 Feb 2018 09:40:34 +0100
Subject: [PATCH] arm64: zynqmp: zcu106: fix SPL MMC booting
The U-Boot SPL generated with the current zcu106 defconfig cannot boot
from MMC:
[...]
U-Boot SPL 2018.01 (Feb 21 2018 - 17:47:14)
EL Level: EL3
Trying to boot from MMC1
sdhci_transfer_data: Error detected in status(0x408020)!
spl_load_image_fat_os: error reading image u-boot.bin, err - -2
spl_load_image_fat: error reading image u-boot.img, err - -6
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix by lowering the rpll value. The new value for the RPLL_CTRL
register comes from the current psu_init_gpl.c from the HDF file at
https://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp
(generated by Vivado v2017.4).
RPLL and sdio1_ref clocks before and after this change:
- Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz
- New values: RPLL 1.16 GHz, sdio1_ref 233 MHz
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Upstream-status: accepted upstream in a different form
---
board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
index 4d18abe000ca..e6fa477e53e7 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
@@ -10,7 +10,7 @@
static unsigned long psu_pll_init_data(void)
{
psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
- psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
--
2.7.4