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Bump buidlroot version to 2018.02.6

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This commit is contained in:
jbnadal
2018-10-22 14:55:59 +02:00
parent 222960cedb
commit bec94fdb63
6150 changed files with 84803 additions and 117446 deletions
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57
bsp/buildroot/arch/Config.in
View File

@@ -79,12 +79,22 @@ config BR2_aarch64_be
config BR2_bfin
bool "Blackfin"
select BR2_ARCH_HAS_FDPIC_SUPPORT
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
help
The Blackfin is a family of 16 or 32-bit microprocessors developed,
manufactured and marketed by Analog Devices.
http://www.analog.com/
http://en.wikipedia.org/wiki/Blackfin
config BR2_csky
bool "csky"
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
select BR2_ARCH_HAS_MMU_MANDATORY
help
csky is processor IP from china.
http://www.c-sky.com/
http://www.github.com/c-sky
config BR2_i386
bool "i386"
select BR2_ARCH_HAS_MMU_MANDATORY
@@ -242,6 +252,37 @@ config BR2_xtensa
endchoice
# For some architectures or specific cores, our internal toolchain
# backend is not suitable (like, missing support in upstream gcc, or
# no ChipCo fork exists...)
config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
bool
config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
bool
default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
# The following symbols are selected by the individual
# Config.in.$ARCH files
config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
bool
config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
# The following string values are defined by the individual
# Config.in.$ARCH files
config BR2_ARCH
@@ -256,6 +297,12 @@ config BR2_GCC_TARGET_ARCH
config BR2_GCC_TARGET_ABI
string
config BR2_GCC_TARGET_NAN
string
config BR2_GCC_TARGET_FP32_MODE
string
config BR2_GCC_TARGET_CPU
string
@@ -284,6 +331,12 @@ config BR2_GCC_TARGET_MODE
config BR2_BINFMT_SUPPORTS_SHARED
bool
# Must match the name of the architecture from readelf point of view,
# i.e the "Machine:" field of readelf output. See get_machine_name()
# in binutils/readelf.c for the list of possible values.
config BR2_READELF_ARCH_NAME
string
# Set up target binary format
choice
prompt "Target Binary Format"
@@ -369,6 +422,10 @@ if BR2_bfin
source "arch/Config.in.bfin"
endif
if BR2_csky
source "arch/Config.in.csky"
endif
if BR2_m68k
source "arch/Config.in.m68k"
endif

4
bsp/buildroot/arch/Config.in.arc
View File

@@ -38,6 +38,10 @@ config BR2_GCC_TARGET_CPU
default "arc700" if BR2_arc770d
default "archs" if BR2_archs38
config BR2_READELF_ARCH_NAME
default "ARCompact" if BR2_arc750d || BR2_arc770d
default "ARCv2" if BR2_archs38
choice
prompt "MMU Page Size"
default BR2_ARC_PAGE_SIZE_8K

337
bsp/buildroot/arch/Config.in.arm
View File

@@ -59,29 +59,42 @@ config BR2_ARM_CPU_ARMV7A
config BR2_ARM_CPU_ARMV7M
bool
config BR2_ARM_CPU_ARMV8
config BR2_ARM_CPU_ARMV8A
bool
choice
prompt "Target Architecture Variant"
default BR2_cortex_a53 if BR2_ARCH_IS_64
default BR2_arm926t
help
Specific CPU variant to use
if !BR2_ARCH_IS_64
comment "armv4 cores"
config BR2_arm920t
bool "arm920t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_arm922t
bool "arm922t"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_fa526
bool "fa526/626"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_strongarm
bool "strongarm sa110/sa1100"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_HAS_MMU_OPTIONAL
comment "armv5 cores"
config BR2_arm926t
bool "arm926t"
select BR2_ARM_CPU_HAS_ARM
@@ -89,14 +102,25 @@ config BR2_arm926t
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_iwmmxt
bool "iwmmxt"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_xscale
bool "xscale"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_HAS_MMU_OPTIONAL
comment "armv6 cores"
config BR2_arm1136j_s
bool "arm1136j-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_arm1136jf_s
bool "arm1136jf-s"
select BR2_ARM_CPU_HAS_ARM
@@ -104,14 +128,12 @@ config BR2_arm1136jf_s
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_arm1176jz_s
bool "arm1176jz-s"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_arm1176jzf_s
bool "arm1176jzf-s"
select BR2_ARM_CPU_HAS_ARM
@@ -119,7 +141,6 @@ config BR2_arm1176jzf_s
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_arm11mpcore
bool "mpcore"
select BR2_ARM_CPU_HAS_ARM
@@ -127,7 +148,8 @@ config BR2_arm11mpcore
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV6
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
comment "armv7a cores"
config BR2_cortex_a5
bool "cortex-A5"
select BR2_ARM_CPU_HAS_ARM
@@ -136,7 +158,6 @@ config BR2_cortex_a5
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a7
bool "cortex-A7"
select BR2_ARM_CPU_HAS_ARM
@@ -145,7 +166,6 @@ config BR2_cortex_a7
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a8
bool "cortex-A8"
select BR2_ARM_CPU_HAS_ARM
@@ -154,7 +174,6 @@ config BR2_cortex_a8
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a9
bool "cortex-A9"
select BR2_ARM_CPU_HAS_ARM
@@ -163,7 +182,6 @@ config BR2_cortex_a9
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a12
bool "cortex-A12"
select BR2_ARM_CPU_HAS_ARM
@@ -172,7 +190,6 @@ config BR2_cortex_a12
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a15
bool "cortex-A15"
select BR2_ARM_CPU_HAS_ARM
@@ -181,7 +198,15 @@ config BR2_cortex_a15
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_cortex_a15_a7
bool "cortex-A15/A7 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
config BR2_cortex_a17
bool "cortex-A17"
select BR2_ARM_CPU_HAS_ARM
@@ -190,14 +215,61 @@ config BR2_cortex_a17
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_cortex_a17_a7
bool "cortex-A17/A7 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_pj4
bool "pj4"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_HAS_MMU_OPTIONAL
comment "armv7m cores"
config BR2_cortex_m3
bool "cortex-M3"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
endif # !BR2_ARCH_IS_64
comment "armv8 cores"
config BR2_cortex_a32
bool "cortex-A32"
depends on !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a35
bool "cortex-A35"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a53
bool "cortex-A53"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a57
bool "cortex-A57"
@@ -205,58 +277,161 @@ config BR2_cortex_a57
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a57_a53
bool "cortex-A57/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a72
bool "cortex-A72"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_m3
bool "cortex-M3"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
depends on !BR2_ARCH_IS_64
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
depends on !BR2_ARCH_IS_64
config BR2_fa526
bool "fa526/626"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_cortex_a72_a53
bool "cortex-A72/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_pj4
bool "pj4"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV3
select BR2_ARM_CPU_ARMV7A
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_cortex_a73
bool "cortex-A73"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_strongarm
bool "strongarm sa110/sa1100"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_cortex_a73_a35
bool "cortex-A73/A35 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_xscale
bool "xscale"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_cortex_a73_a53
bool "cortex-A73/A53 big.LITTLE"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
config BR2_iwmmxt
bool "iwmmxt"
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV5
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_exynos_m1
bool "exynos-m1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
depends on !BR2_ARCH_IS_64
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_falkor
bool "falkor"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_qdf24xx
bool "qdf24xx"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
if BR2_ARCH_IS_64
config BR2_thunderx
bool "thunderx"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_thunderxt81
bool "thunderxt81"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt83
bool "thunderxt83"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt88
bool "thunderxt88"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderxt88p1
bool "thunderxt88p1"
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
endif # BR2_ARCH_IS_64
config BR2_xgene1
bool "xgene1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
if BR2_ARCH_IS_64
comment "armv8.1a cores"
config BR2_thunderx2t99
bool "thunderx2t99"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_thunderx2t99p1
bool "thunderx2t99p1"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
config BR2_vulcan
bool "vulcan"
select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
select BR2_ARM_CPU_HAS_FP_ARMV8
select BR2_ARM_CPU_ARMV8A
select BR2_ARCH_HAS_MMU_OPTIONAL
select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
endif # BR2_ARCH_IS_64
endchoice
config BR2_ARM_ENABLE_NEON
@@ -511,32 +686,60 @@ config BR2_ENDIAN
default "BIG" if (BR2_armeb || BR2_aarch64_be)
config BR2_GCC_TARGET_CPU
# armv4
default "arm920t" if BR2_arm920t
default "arm922t" if BR2_arm922t
default "fa526" if BR2_fa526
default "strongarm" if BR2_strongarm
# armv5
default "arm926ej-s" if BR2_arm926t
default "iwmmxt" if BR2_iwmmxt
default "xscale" if BR2_xscale
# armv6
default "arm1136j-s" if BR2_arm1136j_s
default "arm1136jf-s" if BR2_arm1136jf_s
default "arm1176jz-s" if BR2_arm1176jz_s
default "arm1176jzf-s" if BR2_arm1176jzf_s
default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
default "mpcorenovfp" if BR2_arm11mpcore
# armv7a
default "cortex-a5" if BR2_cortex_a5
default "cortex-a7" if BR2_cortex_a7
default "cortex-a8" if BR2_cortex_a8
default "cortex-a9" if BR2_cortex_a9
default "cortex-a12" if BR2_cortex_a12
default "cortex-a15" if BR2_cortex_a15
default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
default "cortex-a17" if BR2_cortex_a17
default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
default "marvell-pj4" if BR2_pj4
# armv7m
default "cortex-m3" if BR2_cortex_m3
default "cortex-m4" if BR2_cortex_m4
default "fa526" if BR2_fa526
default "marvell-pj4" if BR2_pj4
default "strongarm" if BR2_strongarm
default "xscale" if BR2_xscale
default "iwmmxt" if BR2_iwmmxt
# armv8a
default "cortex-a32" if BR2_cortex_a32
default "cortex-a35" if BR2_cortex_a35
default "cortex-a53" if BR2_cortex_a53
default "cortex-a57" if BR2_cortex_a57
default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
default "cortex-a72" if BR2_cortex_a72
default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
default "cortex-a73" if BR2_cortex_a73
default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
default "exynos-m1" if BR2_exynos_m1
default "falkor" if BR2_falkor
default "qdf24xx" if BR2_qdf24xx
default "thunderx" if BR2_thunderx
default "thunderxt81" if BR2_thunderxt81
default "thunderxt83" if BR2_thunderxt83
default "thunderxt88" if BR2_thunderxt88
default "thunderxt88p1" if BR2_thunderxt88p1
default "xgene1" if BR2_xgene1
# armv8.1a
default "thunderx2t99" if BR2_thunderx2t99
default "thunderx2t99p1" if BR2_thunderx2t99p1
default "vulcan" if BR2_vulcan
config BR2_GCC_TARGET_ABI
default "aapcs-linux" if BR2_arm || BR2_armeb
@@ -546,11 +749,11 @@ config BR2_GCC_TARGET_FPU
depends on BR2_arm || BR2_armeb
default "vfp" if BR2_ARM_FPU_VFPV2
default "vfpv3" if BR2_ARM_FPU_VFPV3
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
default "vfpv4" if BR2_ARM_FPU_VFPV4
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
default "vfpv4" if BR2_ARM_FPU_VFPV4
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
@@ -562,3 +765,7 @@ config BR2_GCC_TARGET_FLOAT_ABI
config BR2_GCC_TARGET_MODE
default "arm" if BR2_ARM_INSTRUCTIONS_ARM
default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
config BR2_READELF_ARCH_NAME
default "ARM" if BR2_arm || BR2_armeb
default "AArch64" if BR2_aarch64 || BR2_aarch64_be

11
bsp/buildroot/arch/Config.in.bfin
View File

@@ -4,14 +4,6 @@ choice
default BR2_bf532
help
Specify target CPU
config BR2_bf606
bool "bf606"
config BR2_bf607
bool "bf607"
config BR2_bf608
bool "bf608"
config BR2_bf609
bool "bf609"
config BR2_bf512
bool "bf512"
config BR2_bf514
@@ -105,3 +97,6 @@ config BR2_GCC_TARGET_CPU_REVISION
value of the -mcpu option. For example, if the selected CPU is
bf609, and then selected CPU revision is "0.0", then gcc will
receive the -mcpu=bf609-0.0 option.
config BR2_READELF_ARCH_NAME
default "Analog Devices Blackfin"

48
bsp/buildroot/arch/Config.in.csky Normal file
View File

@@ -0,0 +1,48 @@
choice
prompt "Target Architecture Variant"
default BR2_ck610
help
Specific CPU variant to use
config BR2_ck610
bool "ck610"
config BR2_ck807
bool "ck807"
config BR2_ck810
bool "ck810"
endchoice
config BR2_CSKY_FPU
bool "Enable FPU coprocessor"
depends on BR2_ck810 || BR2_ck807
help
You can say N here if your C-SKY CPU doesn't have a
Floating-Point Coprocessor or if you don't need FPU support
for your user-space programs.
config BR2_CSKY_DSP
bool "Enable DSP enhanced instructions"
depends on BR2_ck810 || BR2_ck807
config BR2_ARCH
default "csky"
config BR2_ENDIAN
default "LITTLE"
config BR2_GCC_TARGET_CPU
default "ck610" if (BR2_ck610 && !BR2_CSKY_FPU && !BR2_CSKY_DSP)
default "ck807" if (BR2_ck807 && !BR2_CSKY_FPU && !BR2_CSKY_DSP)
default "ck807e" if (BR2_ck807 && !BR2_CSKY_FPU && BR2_CSKY_DSP)
default "ck807f" if (BR2_ck807 && BR2_CSKY_FPU && !BR2_CSKY_DSP)
default "ck807ef" if (BR2_ck807 && BR2_CSKY_FPU && BR2_CSKY_DSP)
default "ck810" if (BR2_ck810 && !BR2_CSKY_FPU && !BR2_CSKY_DSP)
default "ck810e" if (BR2_ck810 && !BR2_CSKY_FPU && BR2_CSKY_DSP)
default "ck810f" if (BR2_ck810 && BR2_CSKY_FPU && !BR2_CSKY_DSP)
default "ck810ef" if (BR2_ck810 && BR2_CSKY_FPU && BR2_CSKY_DSP)
config BR2_READELF_ARCH_NAME
default "CSKY"

3
bsp/buildroot/arch/Config.in.m68k
View File

@@ -35,3 +35,6 @@ endchoice
config BR2_GCC_TARGET_CPU
default "68040" if BR2_m68k_68040
default "5208" if BR2_m68k_cf5208
config BR2_READELF_ARCH_NAME
default "MC68000"

3
bsp/buildroot/arch/Config.in.microblaze
View File

@@ -6,6 +6,9 @@ config BR2_ENDIAN
default "LITTLE" if BR2_microblazeel
default "BIG" if BR2_microblazebe
config BR2_READELF_ARCH_NAME
default "Xilinx MicroBlaze"
config BR2_microblaze
bool
default y if BR2_microblazeel || BR2_microblazebe

80
bsp/buildroot/arch/Config.in.mips
View File

@@ -1,20 +1,30 @@
# mips default CPU ISAs
config BR2_MIPS_CPU_MIPS32
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS32R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS32R6
bool
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS64
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R2
bool
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_CPU_MIPS64R5
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_CPU_MIPS64R6
bool
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
choice
prompt "Target Architecture Variant"
@@ -47,18 +57,23 @@ config BR2_mips_interaptiv
bool "interAptiv"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R2
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_m5150
bool "M5150"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
select BR2_MIPS_NAN_2008
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_m6250
bool "M6250"
depends on !BR2_ARCH_IS_64
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
select BR2_MIPS_CPU_MIPS32R6
config BR2_mips_p5600
bool "P5600"
depends on !BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS32R5
select BR2_MIPS_NAN_2008
config BR2_mips_xburst
bool "XBurst"
depends on !BR2_ARCH_IS_64
@@ -92,9 +107,11 @@ config BR2_mips_i6400
bool "I6400"
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R6
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
config BR2_mips_p6600
bool "P6600"
depends on BR2_ARCH_IS_64
select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
select BR2_MIPS_CPU_MIPS64R6
endchoice
@@ -126,6 +143,64 @@ config BR2_MIPS_SOFT_FLOAT
floating point functions, then everything will need to be
compiled with soft floating point support (-msoft-float).
choice
prompt "FP mode"
depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
default BR2_MIPS_FP32_MODE_XX
help
MIPS32 supports different FP modes (32,xx,64). Information about FP
modes can be found here:
https://sourceware.org/binutils/docs/as/MIPS-Options.html
https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
config BR2_MIPS_FP32_MODE_32
bool "32"
depends on !BR2_MIPS_CPU_MIPS32R6
config BR2_MIPS_FP32_MODE_XX
bool "xx"
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_MIPS_FP32_MODE_64
bool "64"
depends on !BR2_MIPS_CPU_MIPS32
endchoice
config BR2_GCC_TARGET_FP32_MODE
default "32" if BR2_MIPS_FP32_MODE_32
default "xx" if BR2_MIPS_FP32_MODE_XX
default "64" if BR2_MIPS_FP32_MODE_64
config BR2_MIPS_NAN_LEGACY
bool
config BR2_MIPS_NAN_2008
bool
select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
choice
prompt "Target NaN"
depends on BR2_mips_32r5 || BR2_mips_64r5
default BR2_MIPS_ENABLE_NAN_2008
help
MIPS supports two different NaN encodings, legacy and 2008.
Information about MIPS NaN encodings can be found here:
https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html
config BR2_MIPS_ENABLE_NAN_LEGACY
bool "legacy"
select BR2_MIPS_NAN_LEGACY
config BR2_MIPS_ENABLE_NAN_2008
bool "2008"
depends on !BR2_MIPS_SOFT_FLOAT
select BR2_MIPS_NAN_2008
endchoice
config BR2_GCC_TARGET_NAN
default "legacy" if BR2_MIPS_NAN_LEGACY
default "2008" if BR2_MIPS_NAN_2008
config BR2_ARCH
default "mips" if BR2_mips
default "mipsel" if BR2_mipsel
@@ -134,7 +209,7 @@ config BR2_ARCH
config BR2_ENDIAN
default "LITTLE" if BR2_mipsel || BR2_mips64el
default "BIG" if BR2_mips || BR2_mips64
default "BIG" if BR2_mips || BR2_mips64
config BR2_GCC_TARGET_ARCH
default "mips32" if BR2_mips_32
@@ -161,3 +236,6 @@ config BR2_GCC_TARGET_ABI
default "32" if BR2_MIPS_OABI32
default "n32" if BR2_MIPS_NABI32
default "64" if BR2_MIPS_NABI64
config BR2_READELF_ARCH_NAME
default "MIPS R3000"

3
bsp/buildroot/arch/Config.in.nios2
View File

@@ -3,3 +3,6 @@ config BR2_ARCH
config BR2_ENDIAN
default "LITTLE"
config BR2_READELF_ARCH_NAME
default "Altera Nios II"

3
bsp/buildroot/arch/Config.in.or1k
View File

@@ -3,3 +3,6 @@ config BR2_ARCH
config BR2_ENDIAN
default "BIG"
config BR2_READELF_ARCH_NAME
default "OpenRISC 1000"

4
bsp/buildroot/arch/Config.in.powerpc
View File

@@ -212,3 +212,7 @@ config BR2_GCC_TARGET_ABI
default "no-spe" if BR2_PPC_ABI_no-spe
default "ibmlongdouble" if BR2_PPC_ABI_ibmlongdouble
default "ieeelongdouble" if BR2_PPC_ABI_ieeelongdouble
config BR2_READELF_ARCH_NAME
default "PowerPC" if BR2_powerpc
default "PowerPC64" if BR2_powerpc64 || BR2_powerpc64le

3
bsp/buildroot/arch/Config.in.sh
View File

@@ -27,3 +27,6 @@ config BR2_ARCH
config BR2_ENDIAN
default "LITTLE" if BR2_sh4 || BR2_sh4a
default "BIG" if BR2_sh2a || BR2_sh4eb || BR2_sh4aeb
config BR2_READELF_ARCH_NAME
default "Renesas / SuperH SH"

4
bsp/buildroot/arch/Config.in.sparc
View File

@@ -28,3 +28,7 @@ config BR2_GCC_TARGET_CPU
default "leon3" if BR2_sparc_leon3
default "v8" if BR2_sparc_v8
default "ultrasparc" if BR2_sparc_v9
config BR2_READELF_ARCH_NAME
default "Sparc" if BR2_sparc
default "Sparc v9" if BR2_sparc64

15
bsp/buildroot/arch/Config.in.x86
View File

@@ -129,6 +129,15 @@ config BR2_x86_atom
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
config BR2_x86_silvermont
bool "silvermont"
select BR2_X86_CPU_HAS_MMX
select BR2_X86_CPU_HAS_SSE
select BR2_X86_CPU_HAS_SSE2
select BR2_X86_CPU_HAS_SSE3
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
config BR2_x86_k6
bool "k6"
select BR2_X86_CPU_HAS_MMX
@@ -229,6 +238,7 @@ config BR2_ARCH
default "i686" if BR2_x86_corei7_avx && BR2_i386
default "i686" if BR2_x86_corei7_avx2 && BR2_i386
default "i686" if BR2_x86_atom && BR2_i386
default "i686" if BR2_x86_silvermont && BR2_i386
default "i686" if BR2_x86_opteron && BR2_i386
default "i686" if BR2_x86_opteron_sse3 && BR2_i386
default "i686" if BR2_x86_barcelona && BR2_i386
@@ -261,6 +271,7 @@ config BR2_GCC_TARGET_ARCH
default "corei7-avx" if BR2_x86_corei7_avx
default "core-avx2" if BR2_x86_core_avx2
default "atom" if BR2_x86_atom
default "silvermont" if BR2_x86_silvermont
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
@@ -275,3 +286,7 @@ config BR2_GCC_TARGET_ARCH
default "c3" if BR2_x86_c3
default "c3-2" if BR2_x86_c32
default "geode" if BR2_x86_geode
config BR2_READELF_ARCH_NAME
default "Intel 80386" if BR2_i386
default "Advanced Micro Devices X86-64" if BR2_x86_64

30
bsp/buildroot/arch/Config.in.xtensa
View File

@@ -2,39 +2,32 @@ choice
prompt "Target Architecture Variant"
depends on BR2_xtensa
default BR2_xtensa_fsf
config BR2_XTENSA_CUSTOM
select BR2_ARCH_HAS_MMU_OPTIONAL
bool "Custom Xtensa processor configuration"
config BR2_xtensa_fsf
select BR2_ARCH_HAS_MMU_MANDATORY
bool "fsf - Default configuration"
endchoice
config BR2_XTENSA_CUSTOM_NAME
string "Custom Xtensa processor configuration name"
config BR2_XTENSA_OVERLAY_FILE
string "Overlay file for custom configuration"
depends on BR2_XTENSA_CUSTOM
default ""
help
Name given to a custom Xtensa processor configuration.
Enter the path to the overlay tarball for a custom processor
configuration.
config BR2_XTENSA_CORE_NAME
string
default BR2_XTENSA_CUSTOM_NAME if BR2_XTENSA_CUSTOM
default "" if BR2_xtensa_fsf
config BR2_XTENSA_OVERLAY_DIR
string "Overlay directory for custom configuration"
depends on BR2_XTENSA_CUSTOM
default ""
help
Provide the directory path that contains the overlay file
for a custom processor configuration. The path is relative
to the top directory of buildroot.
These overlay files are tar packages with updated configuration
files for various toolchain packages and Xtensa processor
configurations. They are provided by the processor vendor or
directly from Tensilica.
The path can be either absolute, or relative to the top directory
of buildroot.
choice
prompt "Target Architecture Endianness"
depends on BR2_XTENSA_CUSTOM
@@ -54,3 +47,6 @@ config BR2_ENDIAN
config BR2_ARCH
default "xtensa" if BR2_xtensa
config BR2_READELF_ARCH_NAME
default "Tensilica Xtensa Processor"

36
bsp/buildroot/arch/arch.mk.xtensa Normal file
View File

@@ -0,0 +1,36 @@
################################################################################
# This variable can be used by packages that need to extract the overlay.
#
# ARCH_XTENSA_OVERLAY_FILE is the path to the overlay tarball; empty if not
# using any overlay
#
# Example:
# ifneq ($(ARCH_XTENSA_OVERLAY_FILE),)
# tar xf $(ARCH_XTENSA_OVERLAY_FILE) -C $(@D) --strip-components=1 gcc
# endif
################################################################################
BR_ARCH_XTENSA_OVERLAY_FILE = $(call qstrip,$(BR2_XTENSA_OVERLAY_FILE))
ifneq ($(filter http://% https://% ftp://% scp://%,$(BR_ARCH_XTENSA_OVERLAY_FILE)),)
ARCH_XTENSA_OVERLAY_URL = $(BR_ARCH_XTENSA_OVERLAY_FILE)
ARCH_XTENSA_OVERLAY_FILE = $(DL_DIR)/$(notdir $(BR_ARCH_XTENSA_OVERLAY_FILE))
# Do not check that file, we can't know its hash
BR_NO_CHECK_HASH_FOR += $(notdir $(ARCH_XTENSA_OVERLAY_URL))
else
ARCH_XTENSA_OVERLAY_FILE = $(BR_ARCH_XTENSA_OVERLAY_FILE)
endif
################################################################################
# arch-xtensa-overlay-extract -- extract an extensa overlay
#
# argument 1 is the path in which to extract
# argument 2 is the component to extract, one of: gcc, binutils, gdb, linux,
# u-boot
#
# Example:
# $(call arch-xtensa-overlay-extract,/path/to/overlay.tar,$(@D),gcc)
################################################################################
define arch-xtensa-overlay-extract
$(call suitable-extractor,$(ARCH_XTENSA_OVERLAY_FILE)) \
$(ARCH_XTENSA_OVERLAY_FILE) | \
$(TAR) --strip-components=1 -C $(1) $(TAR_OPTIONS) - $(2)
endef